Vertical GaN Transistor Homostructure Design
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Solution Overview
Problem
Existing III-V transistors, such as GaN transistors, face challenges with current collapse and complex contact and metallization designs, particularly in achieving good on-current and low gate capacitance.
Innovation Solution
A vertical III-V transistor design with a gate electrode and channel region within a homostructure, where the channel region is between a first and second portion of the gate electrode, allowing full depletion and reducing capacitive coupling, and featuring a heavily-doped drain region with cavities to minimize gate-to-drain coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a planar HEMT structure is used to form 2DEG at Al(1-x)GaxN/GaN interface, then high electron mobility is achieved, but current collapse occurs and complex metallization design is required
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a vertical three-dimensional structure. The gate electrode is positioned vertically above the channel region, creating a vertical field effect transistor architecture. This dimensional change allows for better electrostatic control and eliminates current collapse while maintaining high electron mobility through the vertical GaN layer structure.
Solution Approach 2:
The patent inverts the conventional planar transistor architecture by placing the gate electrode vertically above the channel rather than laterally adjacent to it. This inversion of the gate-channel spatial relationship creates a vertical FET structure that fundamentally changes the electric field distribution and eliminates the current collapse phenomenon inherent in planar HEMTs.
2Ease of operation
If a lateral FinFET structure is used, then device control is improved, but contact placement and metallization become difficult
Solution Approach 1:
The patent resolves the metallization complexity issue by moving to a vertical architecture where source, drain, and gate contacts can be placed on different vertical levels. This three-dimensional contact arrangement simplifies the metallization design compared to lateral FinFET structures, as contacts can be accessed from the top surface without complex routing around fin structures.
3Productivity
If conventional III-V transistor design is used, then fabrication is achieved, but on-current is insufficient and gate capacitance is high
Solution Approach 1:
The vertical gate structure provides superior electrostatic control over the channel, enabling lower gate capacitance while maintaining strong field effect control. The vertical configuration reduces the gate-to-channel overlap area compared to lateral structures, directly reducing parasitic capacitance and improving switching efficiency.
Solution Approach 2:
The patent utilizes the high electron mobility inherent in GaN material and optimizes the vertical channel dimensions to maximize on-current. The homostructure design with carefully controlled doping profiles in the vertical direction enables high on-current flow while the vertical geometry inherently reduces gate capacitance compared to planar designs.
Data Source
AI summary
An electronic device can include a vertical III-V transistor having a gate electrode and a channel region within a homostructure. The channel region can be disposed between a first portion and a second portion of the gate electrode. In an embodiment, the III-V transistor can be an enhancement-mode GaN transistor, and in a particular embodiment, the drain, source, and channel regions can include the same conductivity type.