Vertical III-N Transistors Decoupling Breakdown Voltage from Lateral Pitch
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Solution Overview
Problem
Conventional lateral GaN power transistors face limitations in scaling due to poor passivation of the III-N surface, leading to premature breakdown under high electric fields, which restricts the reduction of lateral device dimensions for high breakdown voltage applications.
Innovation Solution
The development of vertical III-N power transistors with a lightly-doped drift region and a lateral channel region, where the functional regions with best crystal quality are distal from the substrate, allowing for decoupling of breakdown voltage from lateral dimensions, enabling dimensional scaling through epitaxial growth and self-aligned processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If lateral gate-drain pitch is reduced to enable device scaling, then source-drain pitch can be reduced, but breakdown voltage decreases due to poor surface passivation
Solution Approach 1:
The patent transitions from a lateral device architecture to a vertical device architecture. The drift region extends vertically from the substrate surface through a dielectric layer, creating a three-dimensional structure where the breakdown path is vertical rather than lateral. This dimensional change allows the gate-drain pitch to be reduced while maintaining breakdown voltage, as the vertical drift region provides sufficient breakdown distance independent of lateral dimensions.
2Productivity
If lateral device dimensions are reduced for scaling, then device integration density increases, but surface passivation becomes insufficient leading to premature breakdown
Solution Approach 1:
By moving to a vertical architecture, the patent decouples the breakdown voltage requirement from lateral device dimensions. The vertical drift region provides the necessary breakdown distance in the vertical dimension, allowing lateral dimensions to be reduced for higher integration density without compromising breakdown voltage.
Solution Approach 2:
The patent applies different doping levels to different regions: a lightly-doped drift region for high breakdown voltage, heavily-doped source and drain regions for low contact resistance, and an undoped or lightly-doped channel region for proper transistor operation. This local quality differentiation optimizes each region's function while maintaining overall device performance.
3Length of moving object
If vertical drift region is implemented to decouple breakdown voltage from lateral dimensions, then source-drain pitch can be reduced, but device structure becomes more complex
Solution Approach 1:
The patent segments the device into distinct functional regions: a substrate, a dielectric layer, and a vertical drift region extending through the dielectric. This segmentation allows each region to be optimized independently and simplifies the overall structure by clearly defining functional boundaries rather than requiring complex lateral arrangements.
Solution Approach 2:
The vertical drift region extends in the vertical dimension through the dielectric layer, allowing the source-drain pitch to be reduced in the lateral dimension without compromising breakdown voltage. This dimensional transition simplifies the relationship between breakdown voltage and device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher breakdown voltages and scalable source-drain pitch, enhancing the performance of III-N power transistors for applications like power management ICs and RF power amplifiers by reducing surface passivation issues and improving crystal quality.
Implementation Method 1
A polarization layer 120 is grown over GaN layer 110 forming a two-degree electron gas (2DEG) 111 spanning a lateral spacing L1 between gate electrode 130, source electrode 140, and drain electrode 150
Implementation Method 2
GaN layer 110 is typically 2-5 μm thick. A polarization layer 120 is grown over GaN layer 110
Data Source
AI summary
III-N transistor including a vertically-oriented lightly-doped III-N drift region between an overlying III-N 2DEG channel and an underlying heavily-doped III-N drain. In some embodiments, the III-N transistors are disposed over a silicon substrate. In some embodiments, lateral epitaxial overgrowth is employed to form III-N islands self-aligned with the vertically-oriented drift region. A gate electrode disposed over a portion of a III-N island may modulate a 2DEG within a channel region of the III-N island disposed above the III-N drift region. Charge carriers in the 2DEG channel may be swept into the drift region toward the drain. Topside contacts to each of the gate, source, and drain may be pitch scaled independently of a length of the drift region.