Vertical GaN Transistor Segmentation for Power Reduction
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing power consumption in high-frequency, high-voltage, and high-power applications, particularly in GaN power devices, where existing solutions do not efficiently manage carrier passage and switching.
Innovation Solution
A vertical GaN junction-less power transistor is designed with a drift region, source region, and drain region of the same doping type, featuring a gate electrode and dielectric layers to control carrier passage, reducing power consumption and enabling efficient switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional GaN power devices are used, then high-frequency and high-voltage performance is achieved, but power consumption is high
Solution Approach 1:
The device is segmented into distinct functional regions: source region, drift region, and drain region, with the gate structure dividing the drain region into multiple segments. This segmentation allows independent optimization of each region's function, enabling better control over carrier passage and reduced power consumption while maintaining high-frequency performance
Solution Approach 2:
The gate structure, including gate electrode and gate dielectric layer, acts as an intermediary between the source and drain regions. It controls the passage of carriers through the drift region by creating an electric field that modulates conductivity, thereby reducing power consumption while maintaining switching efficiency
2Use of energy by moving object
If junction-less transistor structure is adopted, then power consumption is reduced, but device complexity increases
Solution Approach 1:
Different regions of the device have locally optimized properties: the source and drain regions are heavily doped while the drift region has lower doping concentration. The gate structure is positioned specifically to control the drift region, creating local variations in electrical properties that reduce overall power consumption without requiring complex global restructuring
Solution Approach 2:
The invention transitions from a planar two-dimensional structure to a three-dimensional vertical structure with the gate wrapping around the drift region. This dimensional change allows the gate to control carrier flow more effectively from multiple directions, reducing power consumption while the vertical integration helps manage structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical transistor effectively reduces power consumption and enhances control over carrier passage, improving the efficiency and performance of GaN power devices in high-power applications.
Implementation Method 1
a gate provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer located between said gate electrode and said drift region
Implementation Method 2
with a first dielectric layer located between adjacent source regions; a second dielectric layer being positioned between said gate electrode and said second surface
Data Source
AI summary
A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.