Vertical Gate Active Pillar Fabrication for Sub-40nm Memory
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Solution Overview
Problem
The existing methods for fabricating semiconductor devices with vertical gates face challenges such as pillar collapse and damage to the upper portion of active pillars during etch-back processes, which hinder the integration of sub-40 nm memory devices and affect the reliability of the semiconductor structure.
Innovation Solution
The method involves forming buried bit lines and active pillars through a series of trench and epitaxial growth processes, where first and second pillar holes are created to bury active pillars, and a gate electrode is formed to surround the pillars, preventing damage and collapse by isolating neighboring gate electrodes and using a tungsten layer for the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If an isotropic etching process is performed to form a recessed sidewall of an active pillar, then the vertical gate structure can be formed, but pillar collapse may occur due to the smaller size of the lower portion compared to the upper portion
Solution Approach 1:
The patent divides the active pillar formation into multiple stages: first forming a lower portion with larger cross-sectional area, then forming the upper portion with smaller cross-sectional area. This segmentation allows the lower portion to provide structural support while the upper portion forms the recessed sidewall, resolving the contradiction between achieving the desired shape and maintaining pillar stability.
Solution Approach 2:
The lower portion of the active pillar is formed in advance with a larger cross-sectional area before forming the upper portion. This preliminary action creates a stable base that prevents collapse during subsequent etching processes, while still allowing the upper portion to achieve the required recessed sidewall shape for vertical gate formation.
2Ease of manufacture
If an oxide etch-back process is performed to form a buried bit line, then the buried bit line can be formed, but the upper portion of the active pillar is damaged
Solution Approach 1:
The patent forms a protective layer on the upper portion of the active pillar before performing the oxide etch-back process. This protective layer acts as a cushion that prevents damage to the upper portion during the etching process, while still allowing the buried bit line to be formed. The protective layer is subsequently removed after serving its protective function.
3Ease of manufacture
If an etch-back process is performed to form a vertical gate, then the vertical gate can be formed, but the upper portion of the active pillar is damaged
Solution Approach 1:
The patent forms a protective layer on the upper portion of the active pillar before performing the etch-back process to form the vertical gate. This protective layer prevents damage to the upper portion during etching, while allowing the vertical gate to be formed. The protective layer is removed after serving its protective function during the gate formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents active pillar collapse and damage during subsequent processes, enabling the stable formation of vertical gate structures suitable for large-scale semiconductor devices with superior operational performance, particularly in sub-30 nm scales.
Implementation Method 1
forming a gate conductive layer over entire surface of a resultant structure including the first active pillars
Implementation Method 2
forming a gate conductive layer over entire surface of a resultant structure including the first active pillars
Implementation Method 3
forming a gate electrode by etching the gate conducting layer to cover the first active pillars
Implementation Method 4
forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode
Data Source
AI summary
A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars.