Vertical Gate-All-Around FET for 10 nm Scaling
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Solution Overview
Problem
As semiconductor devices approach 10 nm or smaller scales, current FinFET architectures become insufficient in maintaining performance due to physical limitations, such as increased surface scattering and higher operating voltages, which affect the channel region and current between the source and drain.
Innovation Solution
A vertical gate-all-around field-effect transistor (GAA FET) is fabricated using a method that involves forming a substrate with dielectric layers, a drain layer, a gate layer, a channel layer, and a source layer, where the source, channel, and drain layers are composed of different materials, allowing for improved control over the channel region and reduced surface scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET architecture is used to increase gate overlapping area, then channel control is improved, but device performance becomes insufficient at 10 nm or smaller scales
Solution Approach 1:
The patent transitions from the planar FinFET architecture to a vertical gate-all-around (GAA) FET structure. This dimensional change allows the gate to wrap completely around the channel in three dimensions, providing superior electrostatic control and enabling continued scaling to 10 nm and below while maintaining adequate performance
2Productivity
If device size is scaled down to 10 nm or smaller, then device density is increased, but surface scattering increases and performance deteriorates
Solution Approach 1:
The patent employs different materials for the source, channel, and drain layers, creating a composite structure. This material composition optimization allows for reduced surface scattering effects while maintaining the benefits of small-scale device density, as each layer can be tailored with specific material properties to mitigate harmful scattering effects
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.