SRAM Cells With Vertical Gate-All-Around MOSFETs for Low Parasitic Capacitance
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Solution Overview
Problem
Existing SRAM cells face challenges in achieving high read and write speeds while maintaining low parasitic capacitance in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) to support high-speed operations.
Innovation Solution
The implementation of Vertical Gate-All-Around (VGAA) transistors in SRAM cells, which feature vertical channels surrounded by gate dielectrics and electrodes, reducing parasitic capacitance and allowing for smaller cell sizes without compromising saturation currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional planar MOSFETs are used in SRAM cells, then manufacturing is simpler, but parasitic capacitance is high which limits read and write speeds
Solution Approach 1:
The patent transitions from planar (2D) MOSFET architecture to vertical (3D) gate-all-around architecture. The gate electrode completely surrounds the channel in all directions, creating a vertical structure that reduces parasitic capacitance by minimizing the overlap between gate and source/drain regions, thereby enabling higher read and write speeds.
Solution Approach 2:
The patent employs FinFET structure where the channel transitions from a planar configuration to vertical fin structures. This phase transition in the channel geometry allows for better electrostatic control and reduced parasitic capacitance while maintaining high-speed operation.
2Speed
If vertical gate-all-around transistors are implemented, then parasitic capacitance is reduced and speed is improved, but device complexity increases
Solution Approach 1:
While the vertical gate-all-around structure does increase structural complexity, the patent manages this by systematically organizing the multi-layer fabrication process and utilizing standard semiconductor manufacturing techniques adapted for 3D structures, thereby achieving the speed benefits while controlling complexity through process integration.
3Productivity
If SRAM cell size is reduced for higher density, then more cells fit in fewer transistors, but maintaining high read and write speeds becomes more difficult
Solution Approach 1:
The vertical transistor structure enables reduced cell size by utilizing the third dimension for device stacking and integration. This allows more SRAM cells to be packed into a smaller area while each cell maintains its high-speed performance through the low-parasitic-capacitance vertical gate-all-around design.
Data Source
AI summary
A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary.