Vertical Gate-All-Around TFET for Low Leakage
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Solution Overview
Problem
Conventional silicon transistors face challenges in maintaining switching speeds and reducing sub-threshold leakage current as device dimensions shrink, leading to increased power consumption and reduced battery life in low-power applications.
Innovation Solution
The implementation of a vertical tunneling field effect transistor (TFET) with a gate-all-around (GAA) device architecture, featuring a nanowire structure oriented transverse to the substrate, with an annular gate surrounding the channel region to control current flow and reduce sub-threshold swing, coupled with electrostatic discharge (ESD) diodes for protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional planar FETs are used, then manufacturing is simple, but switching speed decreases and current leakage increases as device dimensions shrink below 100 nm
Solution Approach 1:
The patent transitions from planar 2D channel structure to a 3D vertical nanowire structure with gate-all-around configuration. This dimensional change enables the gate to control current flow from all directions (top, bottom, and sides), providing superior electrostatic control and faster switching speeds while maintaining compatibility with standard semiconductor manufacturing processes.
Solution Approach 2:
The gate structure completely surrounds the nanowire channel, with the gate oxide layer nested between the gate and the channel. This nested configuration maximizes the gate's control over the channel current by enclosing it from all sides, enabling better electrostatic control and reduced leakage current compared to planar structures.
2Loss of energy
If device dimensions are reduced to increase density, then more transistors fit in smaller volume, but sub-threshold leakage current increases and power consumption rises
Solution Approach 1:
The gate-all-around structure with gate oxide nested between the gate and nanowire channel provides maximum electrostatic control, effectively suppressing sub-threshold leakage current. This configuration allows devices to be scaled to higher densities while maintaining low power consumption due to reduced leakage.
Solution Approach 2:
The patent employs high-k dielectric materials for the gate oxide layer, changing the electrical parameter of the insulator to achieve higher capacitance and better charge control. This parameter change enables effective leakage suppression even at reduced device dimensions and higher densities.
3Reliability
If vertical nanowire structure with gate-all-around is implemented, then switching speed and control are improved, but manufacturing complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential steps: forming the nanowire channel, depositing gate oxide, forming the gate structure, and creating source/drain contacts. This segmentation of the manufacturing process into manageable stages reduces overall complexity while achieving the sophisticated gate-all-around structure.
Solution Approach 2:
The vertical nanowire gate-all-around structure serves multiple functions simultaneously: it provides superior electrostatic control for low leakage, enables fast switching, and maintains compatibility with standard semiconductor fabrication processes. This multi-functionality justifies the enhanced manufacturing complexity by delivering multiple performance benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical TFET provides low-power, high-speed switching performance with enhanced reliability and high current density, suitable for memory applications and low-voltage operations, while the ESD diodes enhance protection against high currents and voltages.
Implementation Method 1
An annular gate surrounds the channel region, capacitively controlling current flow through the channel
Implementation Method 2
During operation of the TFET, charge carriers tunnel through a potential barrier rather than being energized to surmount the potential barrier
Data Source
AI summary
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.