Self-Aligned Vertical Gate-All-Around Transistor Design
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Solution Overview
Problem
The integration density of vertical gate-all-around transistors is limited by the constraints of gate lithography alignment, which poses a yield hazard due to potential misalignment of the gate mask relative to the nanowire, resulting in incomplete gate coverage.
Innovation Solution
The implementation of a self-aligned vertical gate-all-around transistor design that uses a footer portion and a non-footer portion of the gate to ensure complete encirclement of the semiconductor column, even in cases of misalignment, by forming a spacer and etching away unprotected portions of the gate layer to create a ring-like configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gate lithography alignment is used to form the gate around the nanowire, then the gate can be formed using standard lithography processes, but the alignment constraints limit integration density and create yield hazards due to potential misalignment
Solution Approach 1:
The gate footer is formed in advance before the nanowire patterning step. By pre-forming the gate footer structure and then using it as a reference for subsequent nanowire and gate alignment, the patent eliminates the need for precise alignment between the gate mask and nanowire during lithography, thus resolving the contradiction between ease of manufacture and manufacturing precision
Solution Approach 2:
The gate footer serves as a self-aligned reference structure that automatically defines the position and orientation of the gate. The footer's geometry and material properties enable it to guide the formation of the gate without requiring external alignment constraints, making the system self-correcting and eliminating yield hazards from misalignment
2Reliability
If the gate mask is aligned to fully surround the nanowire, then complete gate coverage is achieved, but the alignment constraints limit integration density
Solution Approach 1:
The gate footer is pre-formed with dimensions and positioning that ensure complete nanowire encirclement. This preliminary structure allows the use of tighter gate dimensions and higher density layouts while maintaining reliable gate coverage, as the footer automatically compensates for any alignment variations
Solution Approach 2:
The patent changes the dimensional parameters of the gate structure by introducing the footer portion, which extends the gate's effective coverage area. This parameter change allows for tighter overall gate dimensions while ensuring complete nanowire surround, thus increasing integration density without compromising reliability
Data Source
AI summary
An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first portion of the spacer, etching away an unprotected portion of the structure layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a structure having a footer portion and a non-footer portion, the non-footer portion and the footer portion collectively encircling the semiconductor column, and removing the photoresist and the spacer.