Vertical Gate Electrode Layout to Prevent Connection Portion Collapse

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Solution Overview

Problem

Semiconductor devices face challenges in increasing data processing capacity while reducing component size, requiring enhanced integration of semiconductor elements, which existing vertical transistor structures have not adequately addressed.

Innovation Solution

The semiconductor device incorporates gate electrodes stacked perpendicular to the substrate with varying lengths, subgate electrodes, and dummy channels arranged in specific patterns to improve integration and stability, including first and second dummy channels and isolation regions to support the gate connection portions and prevent structural collapse during manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If vertical transistor structure is adopted to increase integration, then device integration is improved, but structural stability deteriorates due to gate connection portions being vulnerable to collapse

Engineering Contradiction:
Improvedevice integrationVSAvoidstructural stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The gate electrodes are divided into multiple subgate electrodes spaced apart from each other in the second direction. This segmentation reduces the continuous load on gate connection portions while maintaining electrical functionality, thereby preventing structural collapse during manufacturing processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dummy channels are introduced as intermediary structures between real channels and gate connection portions. These dummy channels serve as structural support elements that prevent collapse of gate connection portions during manufacturing, without interfering with the electrical operation of actual transistor channels.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If gate electrodes extend to different lengths to improve integration, then device functionality is enhanced, but manufacturing complexity increases due to varied structures

Engineering Contradiction:
Improvedevice functionalityVSAvoidmanufacturing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Different regions of the gate electrode structure have different properties: subgate electrodes in the first direction have varying lengths to provide different electrical functions, while dummy channels are strategically placed only where structural support is needed. This local differentiation optimizes both functionality and manufacturability without requiring complex structures throughout the entire device.

Inventive Principle:
Principle #3Local quality

3Reliability

If dummy channels are added to prevent structural collapse, then structural stability is improved, but device complexity increases

Engineering Contradiction:
Improvestructural stabilityVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The structural support function is extracted from the main channel structures and implemented separately through dummy channels. These dummy channels are placed only in specific regions where gate connection portions are vulnerable, rather than throughout the entire device, thereby providing necessary support with minimal increase in overall structural complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20240315030A1Semiconductor device
Publication Date: 2024.09.19 SAMSUNG ELECTRONICS CO LTD
  • US20240315030A1 patent drawing
  • US20240315030A1 patent drawing
  • US20240315030A1 patent drawing

AI summary

A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.