Vertical Gate Compound Semiconductor FET for 5G Frequency Scaling
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Solution Overview
Problem
Current compound semiconductor transistors, such as bipolar junction transistors and high electron mobility transistors, are unable to meet the increased transmission frequency requirements of future 5G and 5G+ wireless communication standards due to gate scaling and alignment issues, and rely on expensive materials and processes like electron beam lithography or immersion lithography.
Innovation Solution
A compound semiconductor field effect transistor (FET) with a reduced gate length, fabricated using a method that includes forming an oxide layer, etching through it to create an opening, and depositing conductive gate materials to form a vertical base and head portion of the gate, allowing for self-aligned gates without the need for electron-beam or immersion lithography, enabling a low-cost solution for 5G wireless communications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional compound semiconductor transistors are used, then current 5G transmission frequencies are supported, but future 5G/5G+ performance specifications (ten-fold frequency increase to 28 GHz to 86 GHz) cannot be met
Solution Approach 1:
The gate structure transitions from a planar two-dimensional configuration to a three-dimensional vertical configuration. The gate extends vertically through the dielectric layer and into the channel layer, creating a vertical base portion and head portion that provide enhanced gate control over the channel in the vertical dimension, enabling support for higher transmission frequencies required by future 5G/5G+ specifications
2Speed
If gate length scaling is implemented to meet future 5G specifications, then transmission frequency capability improves, but manufacturing complexity and cost increase due to requirements for electron beam lithography or immersion lithography
Solution Approach 1:
The gate structure is pre-configured during fabrication with a vertical base portion extending through the dielectric layer and a head portion positioned on the dielectric layer. This preliminary formation of the self-aligned gate structure during manufacturing enables subsequent gate length scaling to achieve future 5G frequency requirements without requiring costly electron beam or immersion lithography processes
Solution Approach 2:
The gate structure is designed to be self-aligned, where the vertical base portion and head portion automatically align with the channel during fabrication. This self-alignment eliminates the need for complex alignment processes and expensive lithography techniques, reducing manufacturing cost while enabling the gate length scaling necessary for high-frequency 5G/5G+ operation
3Speed
If gate length is reduced to achieve higher frequency operation, then transmission frequency capability improves, but gate alignment precision becomes more difficult to maintain
Solution Approach 1:
The gate alignment problem is solved by moving from a planar gate configuration to a vertical three-dimensional configuration. The vertical base portion extends downward through the dielectric layer to contact the channel, while the head portion sits on the dielectric layer. This vertical arrangement provides inherent self-alignment that maintains manufacturing precision even as gate length is reduced for higher frequency operation
Solution Approach 2:
The self-aligned gate structure uses the vertical base portion as a self-aligning feature during fabrication. The base portion automatically positions the gate over the channel without requiring high-precision alignment processes, maintaining manufacturing precision while enabling the gate length reduction necessary for supporting higher 5G transmission frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for a low-cost, efficient scaling of gate length to achieve 5G wireless communication capabilities while reducing production costs and improving transmission frequency, overcoming the limitations of existing technologies.
Implementation Method 1
etching through the oxide layer to form an opening
Implementation Method 2
depositing a first conductive gate material at least in the opening to provide a vertical base portion of a gate. The method may also include depositing a second conductive gate material on a portion of the first conductive gate material supported by the oxide layer to provide a head portion of the gate
Data Source
AI summary
A compound semiconductor transistor may include a channel layer. The compound semiconductor transistor may also include a dielectric layer on the channel layer. The compound semiconductor transistor may further include a gate. The gate may include a vertical base portion through the dielectric layer and electrically contacting the channel layer. The gate may also include a head portion on the dielectric layer and electrically coupled to the vertical base portion of the gate.