Vertical Transistor Gate Contacts Using Extended Gate Regions
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Solution Overview
Problem
Traditional planar semiconductor devices face scaling limits, particularly in nonvolatile memory (NVM) and dynamic random access memory (DRAM), leading to high manufacturing costs and limited memory densities, necessitating the use of vertically oriented devices to increase device integration on a chip, where forming gate contacts for vertical transistors poses a significant challenge due to the orientation and topography of semiconductor pillars.
Innovation Solution
Novel structures and methods for gate contact formation in vertical transistors, including extended gate regions, planarized dielectric layers, and merged gates between pillars, which facilitate gate contact formation without additional masking steps and alleviate photolithography challenges, providing sufficient landing pads and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically oriented devices are used to increase device integration on a chip, then memory density is improved, but gate contact formation becomes significantly more difficult due to the orientation and topography of semiconductor pillars
Solution Approach 1:
The patent forms gate contacts in a lateral direction rather than vertically, by creating extended gate regions that protrude outward from the sidewalls of semiconductor pillars. This dimensional shift allows photolithography to pattern gate contacts on a more accessible plane, avoiding the difficulties of vertical contact formation through tall pillar structures.
Solution Approach 2:
The patent performs preliminary actions by forming extended gate regions before final gate contact patterning. These extended regions serve as pre-prepared landing pads that simplify subsequent contact formation, eliminating the need for complex alignment procedures and reducing photolithography challenges.
2Manufacturing precision
If additional masking steps are used to form gate contacts on vertical transistors, then gate contact formation precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the gate contact formation process with existing gate patterning steps by using the same photolithography mask to define both the gate structure and the extended gate region. This integration eliminates additional masking steps while maintaining precise gate contact alignment with the underlying gate structure.
Solution Approach 2:
The photolithography mask serves multiple functions: it patterns the gate structure, defines the extended gate region, and establishes gate contact alignment all in a single step. This multi-functionality reduces manufacturing complexity while preserving the precision needed for gate contact formation.
3Measurement precision
If photolithography is performed directly on tall pillar structures, then gate contact location accuracy is improved, but photolithography challenges increase due to topography
Solution Approach 1:
The patent shifts photolithography from a vertical patterning challenge to a lateral patterning operation by forming extended gate regions that protrude from pillar sidewalls. This creates a more favorable topography for photolithography while maintaining precise gate contact location through the extended region geometry.
Solution Approach 2:
The extended gate region acts as an intermediary structure that bridges the tall pillar and the gate contact. It provides a lateral platform that is easier to pattern with photolithography while maintaining the vertical electrical connection to the pillar, thus mediating between the conflicting requirements of location accuracy and photolithography ease.
Data Source
AI summary
Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.