Vertical Gate Electrode Contacts for Dense NAND Memory Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for semiconductor devices with increased data storage capacity and improved reliability.
Innovation Solution
A semiconductor device design featuring a first semiconductor structure with circuit devices and interconnections, and a second semiconductor structure with vertically stacked gate electrodes, interlayer insulating layers, and contact plugs that electrically connect the gate electrodes to circuit interconnections, including a stack pattern with memory cell and staircase regions, and contact insulating layers to enhance connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked gate electrodes and memory cells are implemented to increase integration density, then data storage capacity is improved, but manufacturing precision requirements worsen due to the complex multi-layer structure
Solution Approach 1:
The patent transitions from planar memory cell arrangement to vertical stacking, where multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) are stacked in the thickness direction to form three-dimensional memory structures. This dimensional change increases storage capacity while the conductive liner and contact insulating layers provide precise alignment references for manufacturing
Solution Approach 2:
The conductive liner acts as an intermediary component between the contact insulating layers and the gate electrodes. It fills the contact hole through the stacked structure and provides a reliable electrical connection path, mediating the complex interface between insulating and conductive layers while maintaining manufacturing precision
2Reliability
If contact plugs penetrate multiple stacked gate electrodes and interlayer insulating layers to improve connectivity, then electrical connectivity is improved, but device complexity worsens due to the multi-layer penetration structure
Solution Approach 1:
The contact structure is segmented into distinct functional components: contact insulating layers (first and second) for insulation, conductive liner for conduction, and contact plugs for connection. Each layer serves a specific function and can be manufactured and controlled independently, reducing overall device complexity while maintaining reliable electrical connectivity through the stacked gate electrodes
Solution Approach 2:
Different regions of the contact structure have different material properties: insulating regions (contact insulating layers) in non-contact areas and conductive regions (conductive liner and contact plugs) in connection areas. This local differentiation of material quality enables precise control of electrical connectivity while simplifying the overall device design by applying appropriate materials only where needed
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A semiconductor device includes a first semiconductor structure including a substrate, circuit devices on the substrate, and circuit interconnections on the circuit devices, and a second semiconductor structure on the first semiconductor structure and having first and second regions. The second semiconductor structure including a plate layer, gate electrodes stacked and spaced apart from each other on an upper surface of the plate layer in a vertical direction, extending by different lengths on the second region in a first direction intersecting the vertical direction, and including a gate contact region, interlayer insulating layers stacked alternately with the gate electrodes, a channel structure penetrating the gate electrodes and the interlayer insulating layers in the first region and extending in the vertical direction, contact plugs penetrating the gate electrodes in the second region, extending in the vertical direction, and electrically connecting the gate electrodes to a portion of the circuit interconnections, respectively.