Vertical Transistor Gate Contacts for Pillar Topography
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Solution Overview
Problem
Traditional planar semiconductor device structures face limitations in achieving high memory densities, leading to the use of vertically oriented transistors, where forming gate contacts is challenging due to the orientation and topography of the semiconductor pillars.
Innovation Solution
The development of novel gate contact formation structures and methods for vertical transistors, including extended gate regions, planarized dielectric layers, and merged gates, which facilitate easier contact formation without additional masking steps and alleviate photolithography challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically oriented transistors are used to increase memory density, then the number of devices per chip increases, but the formation of gate contacts becomes challenging due to pillar orientation and topography
Solution Approach 1:
The patent transitions from traditional planar gate contacts to vertical gate contacts that extend along the sidewalls of semiconductor pillars. The gate structure is formed in a third dimension (vertical) rather than solely in the planar direction, allowing contacts to be made at the top surface of the gate while maintaining connection to the vertically oriented channel
Solution Approach 2:
The gate structure is formed preliminarily before contact formation, with the gate extending vertically along the pillar sidewalls. This preliminary gate structure provides a ready-made target for contact formation at the top surface, eliminating the need to navigate complex pillar topography during contact fabrication
2Manufacturing precision
If self-aligned anisotropic etch with over-etch is used to pattern gates, then gate alignment is improved, but spacer-like gate film pieces are left on pillar sidewalls creating photolithography challenges
Solution Approach 1:
The patent removes the problematic spacer-like gate film pieces from the pillar sidewalls through selective etching processes. These extracted spacer remnants, which would otherwise interfere with subsequent photolithography steps, are eliminated to create a clean surface for mask formation and contact patterning
Solution Approach 2:
The patent introduces intermediate processing steps between gate formation and contact formation, including selective etching and planarization processes. These intermediary steps mediate between the self-aligned gate formation and the subsequent photolithography, removing obstacles and preparing the surface for clean pattern formation
3Ease of manufacture
If traditional planar structures are used, then manufacturing is simpler, but memory density and device integration are limited
Solution Approach 1:
The patent implements a nested structure where vertical semiconductor pillars are formed within a planar substrate, and gates are nested along the pillar sidewalls. This nesting approach allows three-dimensional vertical transistors to be integrated within the traditional planar chip architecture, dramatically increasing device density while maintaining compatibility with existing planar manufacturing processes
Solution Approach 2:
The patent transitions from two-dimensional planar devices to three-dimensional vertical devices by extending the channel and gate structures in the vertical dimension. This dimensional transition allows multiple devices to be stacked vertically within the same footprint, increasing integration density while preserving planar process compatibility
Data Source
AI summary
Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.