Vertical Gate Guard Ring for SPAD Pitch Minimization
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Solution Overview
Problem
Conventional single-photon avalanche diode (SPAD) designs suffer from reduced fill factor and increased dark count rate due to the integration of SPADs and support circuitry on the same chip, limiting miniaturization and packing density.
Innovation Solution
A stacked chip structure is implemented, where SPADs are on a top chip with biased vertical gate structures for guard ring isolation, and support circuitry is on a separate bottom chip, allowing for increased miniaturization and improved edge protection, resulting in higher fill factor and reduced dark count rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SPADs and support circuitry are integrated on the same chip, then device functionality is complete, but fill factor is reduced and packing density is limited
Solution Approach 1:
The device is divided into two separate chips: a first chip containing the SPAD array and a second chip containing the support circuitry. This segmentation allows each chip to be optimized independently, with the SPAD chip achieving high fill factor and the circuitry chip providing complete functionality, thereby resolving the contradiction between functional completeness and fill factor.
2Reliability
If conventional guard ring structures are used, then edge protection is provided, but pitch is increased and packing density is reduced
Solution Approach 1:
The guard ring structure is transformed from a lateral planar structure to a vertical three-dimensional structure by forming a trench and filling it with conductive material. This vertical configuration provides effective edge protection through electric field control while occupying minimal lateral space, thereby reducing pitch and increasing packing density without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked chip structure enhances fill factor and packing density while reducing dark count rates, enabling more efficient photon detection with improved edge protection and miniaturization.
Implementation Method 1
A voltage is applied to the vertical gate structure to generate a depletion region that isolates the single photon avalanche diode from surrounding regions
Implementation Method 2
The SPAD regions have a pn junction that is reverse biased above the breakdown voltage such that a single photo-generated carrier can trigger an avalanche multiplication process
Implementation Method 3
A stacked chip structure includes a first chip and a second chip. The first chip includes a array of single photon avalanche diodes
Data Source
AI summary
A photon detection device includes a single photon avalanche diode (SPAD) including a multiplication junction defined at an interface between n doped and p doped layers of the SPAD in a first region of a semiconductor layer. A vertical gate structure surrounds the SPAD in the semiconductor layer to isolate the SPAD in the first region from a second region of the semiconductor layer on an opposite side of the vertical gate structure. The SPAD laterally extends within the first region of semiconductor layer to the vertical gate structure. An inversion layer is generated in the SPAD around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure. The inversion layer isolates the SPAD from the second region of the semiconductor layer on the opposite side of the vertical gate structure.