Vertical Transfer Gate Image Sensor for Higher Conversion Gain
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Solution Overview
Problem
Current image sensors face limitations in photo sensing capability due to parasitic capacitance between the photo sensing device and the floating diffusion region, which affects conversion gain and overall performance.
Innovation Solution
The image sensor design incorporates a thicker second substrate layer and an inter-substrate insulating layer, with a floating diffusion region and photodiode region spaced apart, reducing parasitic capacitance and enhancing photo sensing capability by using a vertical gate transfer transistor and planar gate reset and source follower transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the photo sensing device and floating diffusion region are placed close together, then the device complexity is reduced, but parasitic capacitance increases which degrades photo sensing capability
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked architecture by placing the photo sensing device in a first substrate layer and the floating diffusion region in a second substrate layer separated by an inter-substrate insulating layer. This vertical stacking in another dimension allows close proximity while maintaining electrical isolation, reducing parasitic capacitance without increasing planar complexity.
Solution Approach 2:
The inter-substrate insulating layer acts as an intermediary between the photo sensing device and the floating diffusion region. This insulating layer physically separates the two components while allowing them to be positioned in close proximity across substrate layers, thereby reducing parasitic capacitance while maintaining structural integration.
2Object-affected harmful factors
If the photo sensing device and floating diffusion region are spaced apart with an insulating layer, then parasitic capacitance is reduced improving photo sensing capability, but the device complexity increases
Solution Approach 1:
By utilizing the vertical dimension through stacked substrate layers, the patent achieves separation of the photo sensing device and floating diffusion region without increasing planar footprint. The inter-substrate insulating layer provides isolation in the vertical direction, reducing parasitic capacitance while maintaining compact integration.
Solution Approach 2:
The inter-substrate insulating layer serves multiple functions simultaneously: it provides electrical isolation to reduce parasitic capacitance, maintains structural support between layers, and enables precise positioning of impurity regions. This multi-functionality reduces the need for additional separate structures.
3Reliability
If a vertical gate penetrates multiple substrate layers, then the transfer transistor performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The gate hole is formed to penetrate through the channel layer and inter-substrate insulating layer before the final gate electrode deposition. This preliminary formation of the gate pathway allows subsequent filling with gate electrode material to create a continuous vertical gate structure that spans multiple layers, improving transistor control while managing manufacturing complexity through staged fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the photo sensing capability by reducing parasitic capacitance and improving conversion gain, leading to enhanced image sensor performance.
Implementation Method 1
parasitic capacitance between the photo sensing device and the floating diffusion region
Data Source
AI summary
An image sensor includes a first substrate layer, a second substrate layer that is thicker than the first substrate layer, an inter-substrate insulating layer arranged between the first substrate layer and the second substrate layer, a first impurity region, a pair of second impurity regions, and a third impurity region, which are spaced apart from each other and arranged on some portions of the first substrate layer. The image sensor further includes a photodiode region constituting a photo sensing device arranged on the second substrate layer, a transfer transistor including a first gate electrode layer that fills a gate hole, penetrates the first substrate layer and the inter-substrate insulating layer, and extends to the second substrate layer, and a floating diffusion region arranged on a side of the first substrate layer and connected to the transfer transistor.