Vertical Gate Line LCD Bezel Reduction
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Solution Overview
Problem
Existing liquid crystal display (LCD) devices face challenges in reducing bezel size due to limitations in manufacturing cost, volume, and aesthetic design, particularly with the Gate-In-Panel (GIP) type, which increases bezel width and restricts the realization of narrow bezels and borderless panels.
Innovation Solution
The implementation of a new gate line structure where vertically formed first gate lines and horizontally formed second gate lines are electrically connected through contacts in an overlapping area, allowing for the removal of link lines from non-display areas and merging gate and data driving logic into a single chip, reducing bezel width by minimizing the common voltage and ground link areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GIP type gate driver is disposed in non-display areas, then manufacturing cost is reduced and volume/weight are reduced, but bezel width increases
Solution Approach 1:
The patent transitions from horizontal gate lines to vertical gate lines in the array substrate, changing the dimensional orientation of the gate driver integration. This vertical arrangement allows the gate driver to be disposed in the non-display area without increasing bezel width, as the gate lines extend vertically from the top edge rather than horizontally from the side edges.
Solution Approach 2:
The patent employs asymmetric arrangement where vertical gate lines are positioned only in the top non-display area rather than distributing gate driver components symmetrically to both left and right sides. This asymmetric configuration reduces bezel width on the longer sides while maintaining functional integrity.
2Volume of moving object
If GIP type gate driver is disposed in non-display areas, then volume and weight are reduced, but bezel width increases
Solution Approach 1:
By changing the orientation of gate lines from horizontal to vertical, the patent utilizes the top non-display area more effectively. This dimensional reorientation consolidates the gate driver functionality into a smaller overall footprint, reducing both volume and bezel width simultaneously.
3Length of stationary object
If link lines are removed from non-display areas, then bezel width is reduced, but electrical connection complexity increases
Solution Approach 1:
The patent extracts and eliminates the link lines that previously connected the gate driver to horizontal gate lines in the non-display area. By removing these intermediate link lines and directly connecting vertical gate lines to the gate driver, the design simplifies the electrical connection structure while reducing bezel width.
Solution Approach 2:
The vertical orientation of gate lines changes the spatial relationship between the gate driver and the pixel array, allowing direct connection without requiring link lines to traverse the non-display area horizontally. This dimensional change inherently simplifies the connection topology.
4Length of stationary object
If common voltage and ground link areas are minimized, then bezel width is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the common voltage line and ground line into a single integrated structure that runs vertically along with the gate lines. This merging reduces the total area occupied by these support lines in the non-display region, thereby minimizing bezel width while maintaining proper electrical connections through unified routing.
Data Source
AI summary
An LCD device includes a plurality of first gate lines and a plurality of data lines vertically formed in a liquid crystal panel, a plurality of second gate lines horizontally formed in the liquid crystal panel, and a plurality of driving ICs disposed in an upper or lower non-display area of the liquid crystal panel, connected to the plurality of first gate lines to supply a scan signal, and connected to the plurality of data lines to supply data voltages. The plurality of first gate lines and the plurality of second gate lines are electrically connected to each other in pairs through a contact in an overlapping area therebetween, and the plurality of first gate lines and the plurality of data lines are formed on different layers.