Vertical Gate Semiconductor Layout for Leakage Isolation
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in achieving improved electrical characteristics and reliability due to the limitations of planar metal oxide semiconductor FETs, particularly in reducing size and enhancing integration.
Innovation Solution
The semiconductor device incorporates insulating patterns with protrusions, a substrate insulating layer, device isolation layers, channel layers, gate structures, and backside contact structures, where the insulating patterns partially penetrate through lower portions of the gate structures, allowing for improved electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulating patterns are provided to improve electrical isolation, then reliability is improved, but leakage currents increase due to insufficient vertical distance
Solution Approach 1:
The insulating patterns are extended in the vertical dimension to partially penetrate through the lower portions of the gate structures. This vertical extension increases the vertical distance between the insulating patterns and the channel layers, thereby reducing leakage currents while maintaining electrical isolation reliability.
Solution Approach 2:
The insulating patterns are strategically positioned to create different vertical distances in different regions. The increased vertical distance is specifically implemented where needed to reduce leakage currents, while maintaining optimal isolation properties in other regions.
2Productivity
If device size is reduced to increase integration, then productivity is improved, but electrical characteristics deteriorate due to reduced spacing
Solution Approach 1:
By utilizing the vertical dimension for insulating pattern penetration, the horizontal spacing between devices can be reduced without compromising electrical characteristics. This enables higher integration density while maintaining proper electrical isolation and device performance.
3Area of stationary object
If backside contact structures are positioned closer to gate electrodes to reduce device footprint, then area is reduced, but short margin is compromised
Solution Approach 1:
The extended vertical insulating patterns create additional spacing in the vertical dimension between backside contact structures and gate electrodes. This allows the device footprint to be reduced while maintaining adequate short margin through the increased vertical separation.
Data Source
AI summary
A semiconductor device includes: insulating patterns spaced apart from each other in a first direction and in a second direction that intersects the first direction; a substrate insulating layer on first side surfaces of the insulating patterns; a device isolation layer on second side surfaces of the insulating patterns; channel layers on the insulating patterns and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the device isolation layer; gate structures vertically overlapping the insulating patterns, surrounding each of the channel layers, and extending in the second direction; source/drain regions provided outside the gate structures; and backside contact structures electrically connected to the source/drain regions and provided below the source/drain regions, wherein the insulating patterns include protrusions protruding in the vertical direction from an upper surface of the device isolation layer, and, in a region in which the insulating patterns vertically overlap the gate structures, a vertical distance between a lower surface of a lowermost channel layer among the channel layers and an upper surface of the protrusions is greater than a vertical distance between the channel layers.