Vertical Gate NAND Array With Segmented Trenches
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Solution Overview
Problem
As critical dimensions of devices in integrated circuits shrink, achieving higher memory density in three-dimensional memory devices becomes challenging due to the difficulty in forming quality memory materials when narrowing the distance between conductive strips, which compromises the quality of memory and gate materials.
Innovation Solution
A method involving the formation of a nonvolatile memory array with alternating semiconductor and insulating layers, where the first set of trenches is wider than the second set, allowing for the deposition of nonvolatile memory material and conductive gate material, while the narrower second trenches are filled with insulating material to separate adjacent stacks, thereby increasing memory density without compromising material quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between adjacent stacks of conductive strips is narrowed to increase memory density, then memory density is improved, but the quality of memory materials and gate material deteriorates
Solution Approach 1:
The patent divides the trench structure into two distinct types: first trenches with wider spacing that receive memory material and gate material, and second trenches with narrower spacing that are filled with insulating material. This segmentation allows the narrow spacing needed for high density to coexist with the wide spacing required for material quality, as each trench type serves a different functional purpose.
Solution Approach 2:
Different regions of the structure are assigned different qualities: first trenches have wider spacing optimized for memory material deposition and gate formation, while second trenches have narrower spacing optimized for electrical isolation. This local differentiation of spacing quality allows simultaneous optimization for both material quality and memory density.
2Quantity of substance
If uniform narrow spacing is used between all adjacent stacks, then memory density is improved, but the ease of manufacture deteriorates due to difficulty in forming quality materials
Solution Approach 1:
The manufacturing process is segmented into two distinct trench formation operations: forming first trenches with wider spacing that facilitate material deposition, and forming second trenches with narrower spacing for isolation. This segmentation of the manufacturing process makes it easier to produce high-quality materials while achieving high memory density, as each trench type is optimized for its specific manufacturing requirements.
Solution Approach 2:
The structure employs local quality differentiation where first trenches have wider spacing optimized for material formation ease, while second trenches have narrower spacing optimized for density. This local variation in spacing quality simplifies the overall manufacturing process by allowing each region to be optimized for its specific function.
Data Source
AI summary
A vertical gate nonvolatile NAND array includes a plurality of vertically stacked NAND strings of nonvolatile memory cells, a plurality of word lines arranged orthogonally over the plurality of vertically stacked NAND strings, and a plurality of vertical columns of conductive gate material electrically coupled to the plurality of word lines. The plurality of vertically stacked NAND strings are with vertically stacked semiconductor strips having opposite sides including a first side and a second side. The vertical columns in the plurality of vertical columns are gates to only one side of the first side and the second side of the opposite sides of the vertically stacked semiconductor strips. The vertical columns in the plurality of vertical columns are gates to adjacent stacks in the plurality of vertically stacked NAND strings.