Vertical Gate 3D NAND Junction Formation via Pull-Back Regions
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Solution Overview
Problem
Existing methods for manufacturing 3D NAND flash memories face challenges in forming high concentration junctions, such as in bit line pads, which are degraded by high thermal processes and require individual implantation steps for each semiconductor layer, increasing manufacturing costs.
Innovation Solution
A method involving the formation of holes through semiconductor layers, followed by an etch process to create pull-back regions, deposition of a second semiconductor material, and ion implantation to establish different doping concentration profiles, resulting in higher conductivity and reducing the need for multiple implantation steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high thermal processes are used to form high concentration junctions in bit line pads, then the junction formation is achieved, but the device performance is degraded
Solution Approach 1:
The patent changes the thermal process parameters by implementing a two-stage annealing approach: first a low-temperature anneal (700-900°C) to form the junction, then a high-temperature anneal (900-1100°C) to activate the dopant. This parameter sequencing resolves the contradiction by achieving junction formation without the detrimental effects of prolonged high-temperature exposure that would degrade device performance.
Solution Approach 2:
The patent performs preliminary doping and low-temperature annealing before the final high-temperature anneal step. This preliminary action establishes the junction structure in advance, allowing the subsequent high-temperature step to focus solely on dopant activation without causing performance degradation from excessive thermal exposure.
2Manufacturing precision
If layer-by-layer implantation is used to form doping concentration profiles in each layer, then different doping profiles are achieved, but the manufacturing cost increases with the number of layers
Solution Approach 1:
The patent merges multiple individual implantation steps into a single blanket implantation step that treats all layers simultaneously. By using the pull-back region structure to define which layers receive doping, the method achieves different doping concentration profiles across layers without requiring separate implantation steps for each layer, thereby reducing manufacturing cost while maintaining doping precision.
Solution Approach 2:
The patent introduces pull-back regions as an intermediary structure that mediates between the blanket implantation process and the selective doping requirement. These regions act as masks or guides that allow a single implantation step to achieve the effect of multiple selective steps, reducing the number of operations required.
3Manufacturing precision
If multiple implantation steps are used for each semiconductor layer, then individual doping control is achieved, but the number of fabrication steps increases
Solution Approach 1:
The patent combines multiple individual layer doping operations into a single blanket implantation step. The pull-back region structures enable this merging by providing spatial selectivity, allowing the process to achieve individual doping control for different layers without requiring separate implantation steps, thus reducing fabrication complexity.
Solution Approach 2:
The patent transitions from a vertical, layer-by-layer doping approach to a horizontal, blanket doping approach. By changing the dimensionality of the doping strategy from sequential (one layer at a time) to parallel (all layers simultaneously), the method reduces the number of steps while maintaining individual layer control through the geometric configuration of pull-back regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the fabrication of high concentration junctions by enhancing conductivity and reducing manufacturing costs through efficient doping concentration profiles and ion implantation techniques.
Implementation Method 1
An etch process is applied to the layers through the holes, to form pull-back regions in the layers adjacent and surrounding the holes
Implementation Method 2
ion implantation can be performed through the openings in the plurality of layers
Data Source
AI summary
A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers. An etch process is applied to the layers through the holes, to form pull-back regions in the layers adjacent and surrounding the holes. A film of second semiconductor material is deposited over the holes and into the pull-back regions. Portions of the film are removed from the holes while leaving elements of the second semiconductor material in the pull-back regions in contact with the first semiconductor material. The holes are filled with insulating material. Layers in the plurality of layers have respective first doping concentration profiles, and the elements of the second semiconductor material in the pull-back regions have second doping concentration profiles. The second doping concentration profiles establish a higher conductivity in the elements of second semiconductor material.