Vertical Gate NAND Memory Cell Segmentation
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Solution Overview
Problem
Existing vertical NAND flash structures have limitations in achieving a smaller cell footprint for a given amount of memory, necessitating further miniaturization to meet demanding applications.
Innovation Solution
The development of a vertical gate NAND memory cell with isolated horizontal channel tracks and multiple memory elements, where each cell includes a charge trap layer and doped polysilicon, and is fabricated using a process involving insulator deposition, trench etching, and polysilicon deposition to form vertical stacks with separate accessible memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical NAND flash structure is used to reduce cell footprint, then memory density is improved, but cell footprint cannot be reduced further for demanding applications
Solution Approach 1:
The memory cell is divided into multiple independently accessible memory elements (first memory element and second memory element) within a single cell footprint. Each element has its own charge trap layer portion and can be accessed separately through different word lines, effectively doubling the storage capacity without increasing the physical cell area.
Solution Approach 2:
The patent transitions from planar memory elements to vertically stacked memory elements. Multiple memory elements are arranged in the vertical dimension rather than spreading them out horizontally, allowing more memory elements to be packed into the same footprint area by utilizing the third dimension (height).
2Quantity of substance
If multiple memory elements are integrated in each cell, then memory density is improved, but device complexity increases
Solution Approach 1:
The vertical gate line serves multiple functions: it acts as a control gate for selecting between the first and second memory elements, and as a common structural element for both elements. This multi-functionality reduces the need for separate control structures for each memory element, thereby managing complexity while enabling multiple elements per cell.
3Ease of manufacture
If vertical gate structure with isolated horizontal channel tracks is used, then manufacturability is improved, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct sequential steps: forming insulator layers, etching trenches, depositing polysilicon, and creating charge trap layers. Each step builds upon the previous one, creating a modular fabrication approach that manages complexity through systematic progression rather than attempting to create the complex structure in a single step.
Data Source
AI summary
In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.