Vertical-Gate Image Sensor for Low-Voltage Photon Counting
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Solution Overview
Problem
Existing image sensors face challenges in operating efficiently at low voltages, which limits their miniaturization and performance in applications such as digital cameras and depth sensing, particularly in achieving single photon counting and three-dimensional imaging.
Innovation Solution
The design incorporates a semiconductor substrate with a vertical gate electrode, charge pocket region, and impurity regions, allowing for efficient photon detection and counting at low voltages through precise control of impurity doping and pixel transistor operations, enabling miniaturization and improved performance in low-illuminance conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional image sensor structures are used, then the sensor can operate at standard voltages, but the sensor size cannot be minimized and low-voltage operation is not achieved
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical three-dimensional structure by positioning the gate electrode above the channel region. This vertical configuration reduces the horizontal footprint of each pixel, enabling sensor miniaturization while maintaining electrical performance for low-voltage operation
Solution Approach 2:
The patent modifies the physical and electrical parameters of the transistor structure, including the vertical gate configuration, doping concentrations in source/drain regions, and channel dimensions. These parameter changes enable the sensor to operate at reduced voltages while achieving compact size
2Volume of moving object
If the sensor is miniaturized, then the sensor size is reduced, but photon detection capability deteriorates
Solution Approach 1:
By moving the gate electrode to a vertical position above the channel, the patent reduces the lateral dimensions of the transistor while preserving the vertical charge collection path. This allows smaller pixel areas without compromising photon detection efficiency
Solution Approach 2:
The patent optimizes the doping profiles and dimensions of specific regions (source, drain, channel) to enhance local electrical properties. This localized optimization ensures efficient charge collection from photon events even in miniaturized structures
3Ease of manufacture
If standard transistor structures are used, then manufacturing is straightforward, but low-voltage operation and single photon counting are not achieved
Solution Approach 1:
The vertical gate structure is integrated into existing semiconductor fabrication processes by adding vertical patterning and deposition steps. This maintains manufacturing feasibility while achieving the enhanced performance needed for single photon counting and low-voltage operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the image sensor to operate effectively at low voltages, facilitating miniaturization and enhancing its ability to detect single photons, thereby improving low-illuminance performance and reducing the size of the sensor while supporting three-dimensional imaging capabilities.
Implementation Method 1
a charge pocket region provided under the vertical gate electrode in the semiconductor substrate, and doped with a first impurity having a first conductivity type
Implementation Method 2
a first impurity region which is spaced apart from the charge pocket region in a vertical direction, doped with a second impurity having a second conductivity type, and surrounded by the vertical gate electrode; and a second impurity region which is provided around the vertical gate electrode and doped with the second impurity
Implementation Method 3
An image sensor is an electronic device that converts an optical image into an electrical signal
Data Source
AI summary
An image sensor includes a semiconductor substrate including a pixel region; a vertical gate electrode disposed in the semiconductor substrate at a center of the pixel region; a charge pocket region provided under the vertical gate electrode in the semiconductor substrate, and doped with a first impurity having a first conductivity type; a first impurity region which is spaced apart from the charge pocket region in a vertical direction, doped with a second impurity having a second conductivity type, and surrounded by the vertical gate electrode; and a second impurity region which is provided around the vertical gate electrode and doped with the second impurity