Vertical Gate-Through Pillar Transistors for Scalable DRAM Wordlines
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Solution Overview
Problem
Current DRAM architectures face challenges in achieving high levels of integration and packing density due to limitations in the configuration of wordlines within memory arrays, which restricts scalability and fabrication complexity.
Innovation Solution
The integration of transistors with conductive gate material passing through pillars of semiconductor material, allowing for wider spacing between wordlines and simplified connections, enabling more efficient and scalable memory array configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM architectures are used with traditional wordline configurations, then fabrication processes are established, but packing density and integration levels are limited
Solution Approach 1:
The gate material extends vertically through the semiconductor pillar rather than horizontally, transitioning from a planar 2D configuration to a 3D vertical configuration. This dimensional change allows wordlines to be spaced wider apart while maintaining transistor functionality, directly increasing packing density without proportionally increasing fabrication complexity
Solution Approach 2:
The gate material is nested within the semiconductor pillar structure, with the gate extending through the entire height of the pillar. This nested configuration integrates the gate function within the existing pillar geometry, enabling higher integration levels while using established fabrication processes
2Quantity of substance
If wordlines are closely spaced to increase integration, then packing density improves, but fabrication complexity and difficulty increase
Solution Approach 1:
By reorienting the gate material to extend vertically through the pillar height rather than horizontally, the design allows wider spacing between wordlines in the horizontal plane. This dimensional reconfiguration maintains high integration levels while simplifying fabrication by reducing the precision requirements for wordline spacing
Solution Approach 2:
The gate material configuration is optimized locally within each pillar, with the gate extending through the specific height of the pillar to provide effective control. This localized optimization allows wider overall wordline spacing while maintaining transistor performance, improving ease of manufacture
Data Source
AI summary
Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.