Vertical Gate Electrode Profiling for Dense 3D Semiconductor Arrays
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to increase integration density while maintaining reliability, which existing technologies struggle to achieve with traditional planar transistor structures.
Innovation Solution
The implementation of a semiconductor device with a vertical transistor structure, featuring alternately stacked gate electrodes and interlayer insulating layers, along with a separation region, and a manufacturing apparatus that alternately supplies deposition and etching gases to form conductive layers with specific thickness profiles, enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical transistor structure is implemented to increase integration density, then the integration density is improved, but the manufacturing complexity increases due to the need for precise alternating stacking of gate electrodes and interlayer insulating layers
Solution Approach 1:
The gate electrode is divided into multiple conductive layers (first conductive layer and second conductive layer) with different thickness profiles. This segmentation allows each layer to serve specific functions: the first conductive layer provides base conductivity while the second conductive layer compensates for thickness variations, thereby simplifying the overall manufacturing process by enabling more robust deposition tolerances
Solution Approach 2:
Different regions of the gate electrode are assigned different thickness characteristics. The first conductive layer has decreasing thickness toward the separation region, while the second conductive layer has increasing thickness toward the separation region. This local quality variation ensures uniform effective gate thickness across different regions, improving device performance while maintaining manufacturability
2Reliability
If conductive layers with sloped surfaces are formed to improve device performance, then the electrical characteristics are improved, but voids may form during deposition reducing reliability
Solution Approach 1:
The gate electrode uses a composite structure of two different conductive layers with complementary thickness profiles. This composite approach allows the formation of sloped surfaces necessary for device performance while the combined structure prevents void formation during deposition, as each layer compensates for the deposition challenges of the other
Solution Approach 2:
The conductive layers are designed with curved thickness profiles rather than sharp transitions. The first conductive layer gradually decreases in thickness while the second conductive layer gradually increases, creating smooth transitions that prevent stress concentration and void formation during deposition, thereby improving both manufacturing precision and device reliability
3Manufacturing precision
If the first conductive layer has decreasing thickness toward the separation region while the second conductive layer has increasing thickness, then uniform effective gate thickness is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The first conductive layer is designed with a thickness profile that pre-compensates for the expected deposition variations. By having the first layer decrease in thickness toward the separation region, it anticipates and counteracts the tendency for material accumulation, allowing the second layer to then increase in thickness and achieve the final uniform effective gate thickness
Solution Approach 2:
The alternating deposition process is structured to first form the first conductive layer with its specific thickness profile, then add the second conductive layer. This preliminary action of forming the first layer with a predetermined non-uniform thickness enables the second layer to be deposited in a way that achieves the desired uniform effective thickness, breaking down a complex single-step process into two more manageable steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased integration density and improved reliability of semiconductor devices by optimizing the structure and manufacturing process, enabling efficient formation of gate electrodes with sloped surfaces and void-free deposition, thus preventing inclination during the manufacturing process.
Implementation Method 1
a first deposition process in which a first process gas of the first deposition gas source and a second process gas of the second deposition gas source are alternately supplied to the process chamber
Implementation Method 2
an etching process in which a third process gas of the etching gas source is supplied to the process chamber
Data Source
AI summary
A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.