Vertical Gate Semiconductor Device Trench Contact Resistance

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Solution Overview

Problem

In vertical gate semiconductor devices, as the distance between trench gate electrodes decreases with miniaturization, the small widths of the source and body regions lead to a reduced contact area, increasing connection resistance with wiring materials.

Innovation Solution

The solution involves forming a recessed portion in the upper part of the trench for the gate electrode, with an insulating film occupying partway, and ensuring the source region and body region contact the wiring layer at the trench wall face, while the body contact region contacts the wiring layer at both the trench wall and substrate surface, with rounded upper corners to prevent voids during material filling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the distance between trench gate electrodes is reduced for miniaturization, then the device density increases, but the contact area between the source/body regions and wiring layer decreases, increasing connection resistance

Engineering Contradiction:
Improvedevice densityVSAvoidconnection resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar contact to three-dimensional contact by forming source and body regions that contact the wiring layer at both the trench wall face and the substrate surface, effectively utilizing vertical dimension to increase contact area without increasing horizontal footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The source and body regions are formed to extend into the trench structure, nesting the contact regions within the three-dimensional space defined by the trench walls and substrate surface, maximizing contact area within constrained lateral dimensions

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the upper corners of the trench wall are rounded, then void formation during material filling is prevented, but the manufacturing process complexity increases

Engineering Contradiction:
Improvevoid preventionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The upper corners of the trench wall are rounded during the trench formation process, before subsequent material deposition, to prevent void formation in advance rather than addressing voids after material filling

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The geometry of the trench wall is modified by rounding the upper corners, changing the physical parameters of the trench structure to improve material flow and prevent void formation during filling

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7518186B2Vertical gate semiconductor device and method for manufacturing the same
Publication Date: 2009.04.14 PANASONIC SEMICON SOLUTIONS CO LTD
  • US7518186B2 patent drawing
  • US7518186B2 patent drawing
  • US7518186B2 patent drawing

AI summary

A gate electrode is buried in a trench passing through a second conductivity type first body region formed on a first conductivity type drain region so as to form a recessed portion at the upper part of the trench. An insulating film is formed on the gate electrode so as to occupy the recessed portion partway. A first conductivity type source region is formed in at least a region of the upper part of the first body region which serves as at least the wall part of the trench. A second conductivity type second body region is formed in the other region of the upper part thereof so as to be adjacent to the source region in the direction that the trench extends. A second conductivity type third body region is formed in the respective upper parts of the source region and the second body region.