Vertical Gate Formation via SOD Etch Rate Modification
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Solution Overview
Problem
The challenge in forming vertical gate structures in semiconductor devices, such as transistors and thyristors, lies in accurately depositing and etching insulator materials within shallow trench isolation (STI) without unintended consumption of hard mask materials or field oxide, which can lead to undesirable effects like mask consumption and etching into unintended areas.
Innovation Solution
The method involves partially filling STI trenches with an insulator material using anisotropic deposition techniques and subsequent modification of spin-on dielectric (SOD) materials to enhance etch rates, allowing for controlled wet etching that selectively removes the SOD material from the trench sidewalls while protecting the insulator material at the bottom, thus avoiding unwanted consumption of mask and field oxide materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching is used to remove insulator material from STI trenches, then the insulator material can be effectively removed, but hard mask material and field oxide are unintentionally consumed
Solution Approach 1:
A spin-on dielectric (SOD) material is introduced as an intermediary layer between the insulator material and the wet etchant. The SOD material has a higher etch rate than the insulator material, allowing it to be selectively removed first while protecting the underlying insulator material and preventing etching of the hard mask and field oxide. This intermediary layer enables precise control over the etching process.
Solution Approach 2:
The patent modifies the etch rate parameter by using a spin-on dielectric material with a specifically engineered etch rate that is faster than the insulator material but slower than the hard mask material. This parameter differentiation allows selective removal of the SOD layer while preserving other critical materials in the structure.
2Manufacturing precision
If dry etching is used to remove insulator material, then selective etching can be achieved, but the process duration causes unwanted consumption of semiconductor and patterning materials
Solution Approach 1:
The spin-on dielectric material serves as a sacrificial intermediary layer that can be rapidly removed via wet etching. This eliminates the need for prolonged dry etching processes, significantly reducing the overall etching time while maintaining selective removal capability. The SOD layer acts as a temporary structure that facilitates the process rather than being the final target.
Solution Approach 2:
The spin-on dielectric material is used as a disposable, sacrificial layer that is intentionally designed to be consumed during the etching process. This temporary material enables the formation of the desired structure without requiring long-duration etching, as it can be quickly removed and does not need to be preserved in the final device.
3Ease of manufacture
If gate structure is formed adjacent to vertical device, then device functionality is achieved, but unwanted removal of hard mask and field oxide occurs
Solution Approach 1:
The spin-on dielectric material is deposited in advance to cover and protect the hard mask and field oxide regions before the gate structure formation process begins. This preliminary protective layer prevents unwanted removal of these materials during subsequent etching and fabrication steps, enabling easier gate structure formation without the harmful side effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise formation of vertical gate structures by ensuring the insulator material is deposited and etched to the desired height without consuming mask or field oxide materials, thereby improving the fabrication process for vertical memory devices like DRAM and T-RAM.
Implementation Method 1
The SOD material can be annealed, for instance, to a temperature that modifies the SOD material and/or converts the SOD material to an oxide, such that the wet etch rate of the modified SOD material is greater than a wet etch rate of the oxide
Implementation Method 2
The modified dielectric material is removed from the trench via a wet etch
Data Source
AI summary
Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.