Vertical Semiconductor Gate Stack Layout for Lower Resistance and Capacitance
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Solution Overview
Problem
Vertical semiconductor devices face challenges with increased resistance and parasitic capacitance as they shrink in size, affecting performance and integration density, particularly due to the arrangement of electrodes and gate stack thickness.
Innovation Solution
A semiconductor device with a gate stack thickness varying perpendicular to the substrate and spacers between the gate stack and source/drain regions to reduce resistance and parasitic capacitance, improving switching performance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of vertical device is reduced to improve integration density, then integration density is improved, but resistance of gate electrode and source/drain region increases
Solution Approach 1:
The gate stack thickness is made non-uniform, with different thicknesses in different regions (first thickness in first region, second thickness in second region). This local variation allows optimization of electrical properties in different areas while maintaining overall device miniaturization for high integration density.
Solution Approach 2:
The thickness parameter of the gate stack is changed from uniform to non-uniform distribution. By adjusting the thickness parameter spatially, the patent achieves reduced resistance in critical regions while maintaining the compact vertical structure needed for high integration density.
2Productivity
If the size of vertical device is reduced to improve integration density, then integration density is improved, but parasitic capacitance between gate electrode and source/drain region increases
Solution Approach 1:
The gate stack thickness is varied locally across different regions to optimize electrical characteristics. The non-uniform thickness distribution allows reduction of parasitic capacitance in overlapping regions while maintaining the compact structure for high integration density.
3Ease of manufacture
If uniform gate stack thickness is used, then manufacturing is simplified, but resistance and parasitic capacitance increase affecting device performance
Solution Approach 1:
The gate stack is designed with different thicknesses in different regions (first thickness in first region, second thickness in second region). This local variation optimizes electrical performance by reducing resistance and parasitic capacitance while remaining manufacturable through standard semiconductor fabrication techniques.
Solution Approach 2:
The gate stack thickness parameter is changed from uniform to non-uniform distribution. This parameter modification reduces resistance and parasitic capacitance, improving device performance while maintaining ease of manufacture through conventional fabrication processes.
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device may include: a substrate; a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other, and a gate stack formed around an outer periphery of the channel region; wherein the gate stack has a thickness varying in a direction perpendicular to a top surface of the substrate.