Vertical Gate Stack Structure for Complete Electrode Filling
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Solution Overview
Problem
Contemporary semiconductor devices face challenges in increasing integration density while maintaining high-speed data processing and compact size, particularly in achieving efficient vertical transistor structures that allow for improved electrical connectivity and reduced material removal issues during manufacturing.
Innovation Solution
The semiconductor device incorporates a stack structure with gate electrodes, interlayer insulating layers, separation patterns, and through-contact plugs on a second substrate, featuring a staircase shape and alternating sacrificial and insulating layers to enhance integration density and electrical connectivity, with barrier patterns to prevent etchant flow and ensure complete filling of conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical transistor structure is employed to increase integration density, then the integration density is improved, but the manufacturing complexity and difficulty of complete filling increase
Solution Approach 1:
The separation structure is divided into multiple patterns (first separation pattern, first barrier pattern, second barrier pattern, second separation pattern) that are segmented and arranged in specific configurations. This segmentation allows for better control of the manufacturing process and ensures complete filling of gate electrodes while maintaining high integration density through the vertical transistor structure.
Solution Approach 2:
The barrier patterns are formed in advance before the gate electrode filling process. This preliminary action prevents etchant flow and ensures that the gate electrodes are completely filled during subsequent manufacturing steps, addressing the filling difficulty while maintaining the vertical structure's integration density benefits.
2Quantity of substance
If gate electrodes are stacked vertically to improve integration density, then the integration density is improved, but incomplete filling of gate electrodes occurs
Solution Approach 1:
Barrier patterns are introduced as intermediary structures between the separation patterns and the gate electrodes. These barrier patterns act as mediators that control etchant flow and prevent incomplete filling of the vertically stacked gate electrodes, ensuring manufacturing precision while maintaining the high integration density of the vertical transistor structure.
Solution Approach 2:
The barrier patterns are positioned to preemptively counteract the harmful effect of etchant flow that would cause incomplete gate electrode filling. By placing these barrier structures in advance, the patent prevents the filling problem before it occurs during the manufacturing process.
3Manufacturing precision
If separation structures are added to ensure complete filling, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
Multiple separation patterns and barrier patterns are merged into a coordinated structure system. The first separation pattern, first barrier pattern, second barrier pattern, and second separation pattern work together as an integrated solution that ensures complete gate electrode filling while managing the overall structural complexity through functional integration.
Data Source
AI summary
A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction.