Vertical Gate Stack Structure for Low-GIDL Semiconductor Scaling
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Solution Overview
Problem
Existing horizontal semiconductor devices face challenges in downsizing due to their parallel arrangement of source, gate, and drain, and they also suffer from high Gate Induced Drain Leakage (GIDL) issues.
Innovation Solution
A vertical semiconductor device is designed with a gate stack comprising a gate dielectric layer, a work function tuning layer, and a gate electrode material layer, where the work function tuning layer is between the gate electrode material layer and the channel region, and a low-k dielectric layer is used to surround a corner of the gate electrode material layer to reduce GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a horizontal device architecture is used with source, gate and drain arranged parallel to substrate surface, then the device structure is conventional and easier to manufacture, but it is difficult to further downsize the device
Solution Approach 1:
The patent transitions from a horizontal device architecture where source, gate and drain are arranged parallel to the substrate surface to a vertical device architecture where these components are arranged perpendicular to the substrate surface. This dimensional change enables further downsizing of the device footprint while maintaining manufacturing feasibility through adapted fabrication processes
2Object-generated harmful factors
If conventional device structure is used, then manufacturing process is standard, but Gate Induced Drain Leakage (GIDL) is high
Solution Approach 1:
The patent introduces a low-k dielectric layer specifically at the corner region where the gate electrode material layer meets the drain region, while other parts of the gate stack maintain conventional materials and structures. This localized modification targets the specific area where GIDL occurs most severely, reducing harmful leakage currents without unnecessarily complicating the entire device structure
Solution Approach 2:
The gate stack employs a composite structure combining conventional gate dielectric layer and work function tuning layer with a low-k dielectric material at the corner region. This composite approach integrates different material properties to simultaneously maintain gate control functionality and reduce GIDL effects in critical areas
Data Source
AI summary
A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.