Vertical Gate Stack Structure for High-Integration Semiconductor Memory
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices poses challenges in achieving higher integration levels, particularly in the vertical disposition of gates rather than traditional two-dimensional arrangements.
Innovation Solution
A semiconductor device design featuring a stack structure with alternately stacked gate layers and interlayer insulating layers in a vertical direction, including vertical structures that penetrate through and contact a pattern structure with a specific layer configuration to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gates are disposed in a vertical direction to increase integration degree, then device integration is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple discrete gate layers (first gate layer, second gate layer, third gate layer) stacked vertically, with each layer independently controllable. This segmentation allows the complex vertical gate structure to be divided into manageable functional units, improving integration while maintaining controllability.
Solution Approach 2:
The patent transitions from traditional two-dimensional planar gate arrangement to three-dimensional vertical stacking, disposing gates in the vertical direction. This dimensional change increases the integration degree by utilizing the vertical space above the semiconductor substrate, allowing multiple gates to occupy a smaller footprint area.
2Productivity
If multiple gate layers are vertically stacked to improve integration, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
Interlayer insulating layers are introduced as intermediary structures between the gate layers. These insulating layers serve as spacing elements and isolation barriers, making it easier to precisely position and form each gate layer independently during manufacturing, thereby reducing the overall manufacturing precision requirements for the stacked structure.
Solution Approach 2:
Different regions of the gate structure have different properties: gate layers in different vertical positions have different conductivity types (n-type, p-type) and functions. This local differentiation allows each layer to be optimized and manufactured with specific requirements, rather than requiring uniform high precision across the entire structure.
3Adaptability or versatility
If vertical structures penetrate through stack structure to contact pattern structure, then device functionality is improved, but reliability challenges arise
Solution Approach 1:
Interlayer insulating layers are placed beforehand between the vertical structures and the gate layers they penetrate. These insulating layers act as cushioning barriers that prevent direct contact and potential short circuits, ensuring reliable electrical isolation while still allowing the vertical structures to penetrate through the stack structure for functional connectivity.
Data Source
AI summary
A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.