Vertical Wrap-Around Gate Transistor Stacking for Smaller Footprints
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Solution Overview
Problem
Existing semiconductor structures with horizontally placed wrap-around gate transistors have conductive channels that occupy a long area in the horizontal direction, limiting the development of semiconductor structures.
Innovation Solution
A semiconductor structure is designed with a substrate, a first transistor placed on the substrate, a second transistor placed vertically above the first transistor, and a gate structure that includes a first and second gate layer connected to each other, surrounding both transistors, with their extension directions perpendicular to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If horizontally placed wrap-around gate transistors are used, then the transistor structure is simple to manufacture, but the conductive channel occupies a long area in the horizontal direction
Solution Approach 1:
The patent transitions from horizontal transistor arrangement to vertical stacking, changing the spatial dimension from 2D planar layout to 3D vertical architecture. This allows multiple transistors to be stacked above each other, reducing the horizontal area occupied while maintaining functionality through vertical integration of gate structures and conductive channels
2Length of moving object
If horizontally arranged transistors are used, then the device layout is simple, but the conductive channel length is insufficient for high performance
Solution Approach 1:
The invention extends the conductive channel length by stacking transistors vertically, allowing the channel to extend through multiple vertical layers rather than being constrained to horizontal plane. This enables longer effective channel length for improved transistor performance without proportionally increasing the horizontal device footprint
Data Source
AI summary
The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a first transistor, located on the substrate; a second transistor, located above the first transistor; and a gate structure, the gate structure including a first gate layer and a second gate layer, which connected to each other, the first gate layer surrounding the first transistor and the second gate layer surrounding the second transistor; an extension direction of the first transistor and an extension direction of the second transistor are both perpendicular to the substrate.