Vertical Gate-All-Around Transistor Structure for Higher Density
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving improved electrical characteristics and integration density while maintaining high reliability and multifunctionality.
Innovation Solution
The semiconductor device incorporates an active pattern with long sidewalls and a gate electrode extending along these sidewalls, along with epitaxial patterns and spacers, to enhance electrical performance and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planar transistor structures are used, then manufacturing process is simple, but electrical characteristics and integration density are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) structures by extending the channel length in the vertical direction. The active pattern protrudes from the substrate with height H, and the gate electrode wraps around the sidewalls, creating a vertical field effect transistor that achieves improved electrical characteristics through increased effective channel area without proportionally increasing footprint area.
Solution Approach 2:
The gate electrode is configured to wrap around and contact the sidewalls of the active pattern, creating a nested structure where the gate surrounds the channel region. This all-around gate configuration enables better electrostatic control and improved electrical characteristics while maintaining compact integration.
2Productivity
If transistor size is reduced to improve integration density, then more devices fit on chip, but manufacturing precision and electrical characteristics deteriorate
Solution Approach 1:
By extending the transistor structure vertically with height H, the patent increases the effective channel area without increasing the lateral footprint. This allows higher integration density while maintaining adequate channel dimensions for reliable electrical characteristics, as the vertical dimension compensates for the reduced planar area.
Solution Approach 2:
The patent employs selective epitaxial growth to create composite semiconductor structures with different materials (e.g., SiGe source/drain regions with silicon channel). This enables precise control of electrical characteristics through material composition optimization while maintaining small feature sizes for high integration density.
3Manufacturing precision
If vertical field effect transistor structure is implemented, then electrical characteristics and integration density are improved, but manufacturing process complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming the active pattern with protruding structure, performing selective epitaxial growth for source/drain regions, depositing gate electrodes, and creating contact holes. This segmentation of the manufacturing process into manageable steps reduces overall complexity compared to attempting to create the entire vertical structure in one process.
Solution Approach 2:
The active pattern is formed in advance with the protruding vertical structure before subsequent epitaxial growth and gate deposition. This preliminary formation of the vertical architecture simplifies later processing steps, as the three-dimensional structure is already in place to guide subsequent material deposition and patterning operations.
Data Source
AI summary
There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.