3D Semiconductor Transistor Structure for Dense Memory Isolation
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Solution Overview
Problem
The increasing demand for higher storage capacity in non-volatile memory devices, such as flash memory, necessitates more efficient use of storage space, which existing technologies do not adequately address, particularly in terms of electrical characteristics and integration in semiconductor devices.
Innovation Solution
A semiconductor device with a substrate featuring protrusions and trenches, where gate patterns are formed with device isolation layers and spacers made of the same material, allowing for improved electrical characteristics and integration by aligning sidewalls and filling trenches to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a planar transistor structure is used, then the device structure is simple and easy to manufacture, but the storage capacity and integration density are limited
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical (3D) transistor structure by forming protrusions that extend upward from the substrate surface. Gate patterns are formed on the sides of these protrusions, creating a vertical channel that increases the effective channel area without increasing the footprint area, thereby improving integration density and storage capacity.
Solution Approach 2:
The substrate surface is segmented into multiple protrusions arranged in an array, with each protrusion serving as an independent transistor unit. This segmentation allows for high-density integration while maintaining simple individual transistor structures, resolving the contradiction between complexity and productivity.
2Productivity
If transistors are placed closer together to increase integration density, then storage capacity improves, but signal interference between adjacent transistors increases
Solution Approach 1:
Device isolation layers are formed between adjacent protrusions and gate patterns to electrically isolate individual transistors. This extraction of the isolation function into a dedicated layer prevents signal interference between closely spaced transistors while maintaining high integration density.
Solution Approach 2:
The device isolation layers act as intermediary elements between adjacent transistor structures, providing electrical isolation that prevents harmful signal interference while allowing the transistors to be placed in close proximity for high-density integration.
3Ease of manufacture
If device isolation layers and spacers are formed with different materials, then material selection flexibility is high, but manufacturing complexity and process steps increase
Solution Approach 1:
The device isolation layers and spacers are formed using the same material, merging these two previously separate material selections into one. This reduces the number of material deposition processes and simplifies the manufacturing workflow while maintaining the functional benefits of both isolation and spacing structures.
Solution Approach 2:
A single material is used to perform multiple functions: forming both the device isolation layers that electrically isolate transistors and the spacers that define gate pattern dimensions. This multi-functionality approach simplifies the manufacturing process by eliminating the need for separate material deposition steps.
Data Source
AI summary
A semiconductor device include a substrate including a plurality of protrusions protruding from an upper surface thereof and arranged two-dimensionally in a first direction and a second direction intersecting each other, a first trench provided between the protrusions in the first direction, and a second trench provided between the protrusions in the second direction, a first device isolation layer filling the first trench, gate patterns disposed on the protrusions in the second direction, upper surfaces of the protrusions exposed at both sides of the gate patterns, respectively, and a second device isolation layer filling a space between the gate patterns in the second direction and the second trench, and each of the gate patterns has a first sidewall adjacent to the second trench and aligned with an inner wall of the second trench.