Vertical Gate Fabrication via Trench Separation and Epitaxial Growth
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices with vertical gates face challenges in preventing misalignment between active pillars and trenches, and damage to protective layers during the trench formation process, which affects the accuracy and integrity of buried bit lines.
Innovation Solution
A method involving the formation of buried bit lines followed by a trench separation process before active pillar formation, using multiple masks and etch barriers to ensure precise alignment and protect the layers, including the use of interlayer insulation and epitaxial growth for substrate formation, and etching processes with specific mask patterns to prevent misalignment and layer damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the trench formation process is performed after the active pillar is formed, then the misalignment between active pillar and trench can be detected, but the protective layer may be damaged and overlay occurs during etching
Solution Approach 1:
The patent applies preliminary action by forming the trench to separate buried bit lines BEFORE forming the active pillars. This sequence prevents the protective layer damage and overlay issues that occur when trench formation is performed after active pillar formation. The trench is created first using a photoresist mask, then the active pillars are formed subsequently, eliminating the harmful effects of misalignment and protective layer damage during etching.
2Measurement precision
If the trench formation process is performed after the active pillar is formed, then the misalignment can be found, but the process complexity increases due to multiple masks and etch barriers
Solution Approach 1:
The patent applies inversion by reversing the conventional process sequence. Instead of forming active pillars first and then trenches, the trench formation is performed first to separate buried bit lines, followed by active pillar formation. This inverted sequence simplifies the overall process by eliminating the need for complex multiple mask and etch barrier procedures, while still achieving precise alignment.
3Manufacturing precision
If multiple masks and etch barriers are used to ensure precise alignment, then manufacturing precision improves, but the fabrication process becomes more complex
Solution Approach 1:
The patent achieves high manufacturing precision through preliminary action by forming the trench structure before active pillar formation. This preliminary trench formation establishes precise alignment references that guide subsequent active pillar fabrication, eliminating the need for multiple complex masks and etch barriers while maintaining high alignment precision throughout the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents misalignment and damage, enabling stable and accurate formation of active pillars and vertical gates, thereby improving the fabrication process for semiconductor devices with vertical gates.
Implementation Method 1
a buried bit line (BBL) is formed by performing an ion implantation process
Implementation Method 2
an active pillar 12 having recessed sidewalls is formed by etching a substrate 11
Implementation Method 3
epitaxial growth for substrate formation
Data Source
AI summary
A method for fabricating a semiconductor device includes forming buried bit lines in a first substrate; forming a trench that separate the buried bit lines from each other; forming an interlayer insulation layer to gap-fill the trench; forming a second substrate over the first substrate gap-filled with the interlayer insulation layer; forming a protective pattern over the second substrate; forming a plurality of active pillars by etching the second substrate using the protective pattern as an etch barrier; and forming vertical gates surrounding sidewalls of the active pillars.