Vertical Gated Diode Fabrication via Gate-Last Process Integration
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Solution Overview
Problem
There is a need for a method to fabricate vertical gated diodes that is compatible with the gate-last process flow used for forming vertical FETs, as existing methods do not efficiently integrate these components.
Innovation Solution
A semiconductor structure is formed with a first doped semiconductor segment of one conductivity type extending from a doped bottom layer, a second doped semiconductor segment of opposite conductivity type, a doped top semiconductor region laterally surrounding the second segment, and a gate structure surrounding both segments, achieved through a series of epitaxial growth and etching processes within a trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional fabrication method is used for gated diodes, then the diode structure can be formed, but it is not compatible with the gate-last process flow used for vertical FETs
Solution Approach 1:
The patent applies universality by designing a fabrication process that serves dual purposes: it can form both vertical FETs and vertical gated diodes using the same gate-last process flow. The method uses a sacrificial gate layer that can be selectively removed in diode regions while being retained in FET regions, allowing one process to accomplish multiple device formations without requiring separate fabrication sequences.
Solution Approach 2:
The patent introduces a sacrificial gate layer as an intermediary element that facilitates the formation of gated diodes within the gate-last process flow. This sacrificial layer temporarily occupies the gate position during fabrication, allowing subsequent steps to proceed uniformly for both FETs and diodes. The sacrificial material is later selectively removed in diode regions to create the gated diode structure, acting as a mediator that enables process compatibility.
2Productivity
If vertical FETs are formed using gate-last process flow, then density scaling and electrostatics control are improved, but integration of gated diodes becomes difficult
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor structure into distinct regions: FET regions where the gate layer is retained, and diode regions where the gate layer is removed to form p-n junctions. This spatial segmentation allows both device types to coexist within the same gate-last process flow, enabling gated diodes to be integrated alongside vertical FETs without compromising the density scaling and electrostatics control benefits of the gate-last approach.
3Adaptability or versatility
If gated diodes are integrated with vertical FETs, then circuit functionality is enhanced, but fabrication process compatibility is reduced
Solution Approach 1:
The patent applies preliminary action by forming the p-n junction structure of the gated diode before the final gate electrode is deposited. The sacrificial gate layer is removed in diode regions early in the process, allowing the p-n junction to be formed in advance. This preliminary formation of the diode structure enables subsequent uniform processing for both FETs and diodes, maintaining process compatibility while achieving enhanced circuit functionality through the integration of both device types.
Data Source
AI summary
After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.