Vertical Gate Structures Around Semiconductor Pillars for Stronger Coupling
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Solution Overview
Problem
Current integrated circuit fabrication methods face challenges in achieving strong coupling between conductive gates and channel regions in transistors, particularly in vertically-extending semiconductor material pillars, which affects integration density and device scaling.
Innovation Solution
The method involves forming conductive lines that wrap partially or entirely around semiconductor material pillars, with initial alternating layers of semiconductor and insulative materials, where the insulative material is recessed to create trenches for conductive line formation, ensuring substantial vertical sidewalls and effective gate-channel coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used with horizontally-extending gates, then manufacturing process is simpler, but gate-channel coupling strength is insufficient for high-density integration
Solution Approach 1:
The patent transitions from conventional horizontal gate extension to vertical gate wrapping around semiconductor pillars. This dimensional change enables the gate to surround the channel region in three dimensions, dramatically improving gate-channel coupling strength while accommodating higher integration densities through the vertical architecture
2Productivity
If integration density is increased through device scaling, then circuit functionality is enhanced, but fabrication precision requirements increase
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming alternating semiconductor and insulative layers, selectively recessing insulative material to create trenches, depositing conductive gate material, and planarization. This segmentation allows each step to be optimized independently, managing fabrication precision requirements while achieving high integration density
Solution Approach 2:
The alternating layers of semiconductor and insulative materials are formed in advance before the gate structure is created. This preliminary action establishes the vertical architecture and spacing requirements upfront, enabling subsequent gate formation with appropriate precision controls
Data Source
AI summary
Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.