Vertical Power Delivery Layout for High-Density GPU Power Phases
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Solution Overview
Problem
Conventional flattened power delivery systems for processors, such as GPUs, are limited by large power phase sizes, leading to inefficiencies and constraints in power consumption, especially for complex processors like GPUs used in AI training, and result in increased power loss due to larger processor packages.
Innovation Solution
The implementation of vertical multi-function power delivery devices using an inductor with mounted DrMOS modules and capacitors, which provide a compact and efficient power delivery solution by reducing size and enhancing power density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional flattened power delivery is used, then power phases can be placed around the processor, but the power phase sizes are large relative to processor sizes, limiting the number of power phases that can be placed
Solution Approach 1:
The patent transitions from a conventional flattened (2D) power delivery layout to a vertical (3D) architecture. Power phases are stacked vertically above the processor rather than being placed around it in the same plane, effectively utilizing the third dimension to increase power delivery capacity without increasing the footprint area.
Solution Approach 2:
The vertical power delivery architecture nests power phases vertically above the processor core, similar to nested dolls. Multiple power phases are stacked in layers, with each layer containing power delivery components that are vertically positioned over the processor, maximizing space utilization.
2Productivity
If processor packages are increased in size to provide greater computing performance, then more execution circuitry and memory sites can be placed within the package, but the distances between power phases and processor core power rails increase, resulting in increased power loss
Solution Approach 1:
By moving power phases to a vertical stacking architecture, the horizontal distance between power phases and processor power rails is eliminated. Power is delivered vertically through short interconnects directly from the power phase layer to the processor layer, minimizing resistive losses regardless of processor package size.
Solution Approach 2:
The patent introduces vertical interconnect structures as intermediaries between the power phases and processor power rails. These specialized interconnects serve as efficient power transmission pathways, reducing power loss by providing low-resistance vertical power delivery paths through the package.
3Power
If conventional flattened power delivery is used, then power can be delivered to the processor, but the power phases are large in size, constraining the number of power phases that can be placed around the processor
Solution Approach 1:
The patent simplifies the overall power delivery architecture by moving to vertical stacking, which consolidates multiple power phases into compact vertical modules. This reduces the horizontal space required and allows higher power delivery capacity within a smaller footprint, effectively managing complexity through dimensional reorganization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed power delivery devices enable higher power delivery capacity and improved efficiency by allowing a larger number of devices to be placed under the processor, reducing size and increasing power density compared to conventional methods.
Implementation Method 1
a power delivery device includes an inductor
Data Source
AI summary
One embodiment of a power delivery device includes an inductor and one or more chips that are mounted on top of the inductor. One embodiment of a graphics card includes a graphics processing unit (GPU) mounted on top of a first side of a circuit board, and one or more power delivery devices mounted on top of a second side of the circuit board. Each power delivery device included in the one or more power delivery devices includes an inductor and one or more chips disposed on top of the inductor.