Vertical-Grain Transistor Channel for Higher Current Flow
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Solution Overview
Problem
Existing transistor technologies face challenges in achieving optimal current flow and operational characteristics due to limitations in crystal grain size and alignment in the channel region.
Innovation Solution
The development of transistors with a channel region comprising vertically-elongated crystal grains that directly contact both the top and bottom source/drain regions, along with varying average crystal grain sizes between the channel and source/drain regions, to enhance current flow and operational control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor channel structures are used, then manufacturing is simpler, but current flow and operational characteristics are suboptimal
Solution Approach 1:
The channel region is segmented into multiple vertically-elongated crystal grains rather than a single continuous structure. This segmentation creates direct contact pathways between source/drain regions while maintaining manufacturability through controlled crystal growth processes.
Solution Approach 2:
The channel region exhibits local quality variations through differently oriented crystal grains in different areas. This allows optimization of current flow in specific regions while maintaining overall structural integrity and manufacturability.
2Reliability
If crystal grain size is increased, then current flow improves, but alignment control becomes more difficult
Solution Approach 1:
The solution transitions from planar crystal grain structures to vertically-elongated three-dimensional structures. This dimensional change allows larger effective grain sizes that improve current flow while the vertical orientation provides natural alignment references that simplify manufacturing control.
Solution Approach 2:
The crystal grains exhibit asymmetric elongation in the vertical direction rather than uniform isotropic growth. This asymmetric geometry inherently guides alignment during manufacturing while providing the large cross-sectional area needed for optimal current flow.
Data Source
AI summary
A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.