Vertical Graphene Interconnect Structure for Void-Free Narrow Openings
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Solution Overview
Problem
Current semiconductor interconnect technologies face challenges in forming reliable and conductive structures within narrow, high-aspect-ratio openings, often resulting in voids and high resistance due to grain boundaries in metal deposition, which hinders the miniaturization and performance of integrated circuits.
Innovation Solution
A method involving the formation of a graphene conductive structure by depositing graphene layers parallel to the inner lateral surface of dielectric layers within interconnect openings, using techniques like PECVD, and optionally doping or intercalating materials to enhance conductivity, allowing for gap-free filling of small to large openings without the limitations of metal deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal deposition is used to form interconnect structures, then electrical conductivity is achieved, but voids and high resistance occur due to grain boundaries
Solution Approach 1:
The patent extracts the problematic metal deposition process and replaces it with a graphene-based conductive structure formed through chemical vapor deposition. This removes the source of grain boundary-related voids and high resistance while maintaining the essential function of electrical conduction in interconnect structures.
Solution Approach 2:
The patent changes the material parameter from traditional metals to graphene, fundamentally altering the deposition mechanism and microstructure formation. This parameter change eliminates grain boundary formation while achieving superior electrical conductivity and void-free structures in high-aspect-ratio interconnect openings.
2Ease of manufacture
If traditional metal deposition is used, then interconnect structures can be formed, but the process becomes limited as device dimensions shrink
Solution Approach 1:
The patent changes the material system from conventional metals to graphene, enabling effective miniaturization. The unique properties of graphene allow for scalable fabrication across varying device dimensions without the limitations that constrain traditional metal deposition processes in nanoscale applications.
Solution Approach 2:
The patent employs graphene as a composite conductive material within the interconnect structure, combining the benefits of high conductivity with superior fillability in high-aspect-ratio openings. This composite approach overcomes the scaling limitations of pure metal deposition.
3Manufacturing precision
If graphene layers are deposited parallel to the inner lateral surface, then gap-free filling is achieved, but deposition technique complexity increases
Solution Approach 1:
The patent replaces conventional physical vapor deposition mechanisms with chemical vapor deposition processes that enable graphene layers to conformally coat the inner lateral surfaces. This substitution achieves gap-free filling through chemical reaction and self-assembly mechanisms rather than traditional physical deposition, improving fill quality despite increased process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The graphene conductive structure effectively fills interconnect openings of varying sizes without voids, provides robust electrical conductivity, and maintains durability, overcoming the limitations of traditional metal deposition methods, especially as device dimensions shrink.
Implementation Method 1
depositing graphene layers parallel to the inner lateral surface of dielectric layers within interconnect openings, using techniques like PECVD
Data Source
AI summary
A semiconductor structure includes a substrate, a dielectric layer, and a graphene conductive structure. The dielectric layer is disposed on the substrate, and has an inner lateral surface that is perpendicular to the substrate. The graphene conductive structure is formed in the dielectric layer and has at least one graphene layer extending in a direction parallel to the inner lateral surface of the dielectric layer.