Vertical Half-Bridge Circuit Segmentation for Inductance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Half-bridge converters face inefficiencies due to high parasitic inductance and gate resistance, leading to slower turn-on times and increased conduction losses, especially in large switches, which exacerbate issues like voltage overshoot and reduced yield with switch size.
Innovation Solution
The implementation of a vertical power loop half-bridge circuit with microstrip transmission lines and vias to reduce inductance, utilizing substrates like BeO with high thermal conductivity and precise metallization, and eliminating bond wires to minimize inductance and thermal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If switch size is increased to handle higher power, then power handling capability is improved, but parasitic inductance and gate resistance increase causing slower turn-on times
Solution Approach 1:
The switch is divided into multiple parallel cells (e.g., 6 cells in parallel) to handle higher power while maintaining lower parasitic inductance and gate resistance. Each cell operates independently, allowing the total power handling capability to scale without proportionally increasing the parasitic elements that limit switching speed.
2Power
If switch size is increased to handle higher power, then power handling capability is improved, but voltage overshoot increases due to increased power loop inductance
Solution Approach 1:
The power loop is segmented into multiple parallel paths through the use of multiple switch cells. This segmentation reduces the effective inductance of the power loop by distributing the current across multiple parallel paths, thereby reducing voltage overshoot during switching transitions while maintaining high power handling capability.
3Reliability
If gate width is increased to reduce gate resistance, then gate resistance is reduced, but switch area and cost increase
Solution Approach 1:
The gate structure is segmented into multiple parallel gate connections for each cell. This segmentation allows the gate resistance to be reduced by providing multiple parallel current paths to the gate, without requiring a single large gate width that would increase the overall switch area and cost.
4Power
If switch size is increased to handle higher power, then power handling capability is improved, but switch yield decreases rapidly
Solution Approach 1:
The switch is implemented as multiple smaller cells in parallel rather than a single large switch. This segmentation improves yield because smaller cells have lower defect density and higher manufacturing yield. The parallel configuration allows the overall power handling capability to be achieved through multiple smaller, more reliable units.
5Reliability
If wider feed traces are used to reduce feed resistance, then feed resistance is reduced, but switch area and on-resistance product increase
Solution Approach 1:
The feed path is segmented into multiple parallel traces, one for each cell. This segmentation reduces the feed resistance by providing multiple parallel current paths without requiring a single wide trace that would consume excessive switch area and increase the on-resistance product.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces switching times, minimizes ringing, and increases switch yield by effectively canceling magnetic fields and decreasing parasitic capacitance, enabling faster and more efficient high-current switching with reduced voltage overshoot.
Implementation Method 1
effectively canceling magnetic fields and decreasing parasitic capacitance
Implementation Method 2
utilizing substrates like BeO with high thermal conductivity
Data Source
Figure 1
Figure 2
Figure 3A~3D
AI summary
A half bridge circuit including an isolation substrate, a metal layer on one surface of the isolation substrate, a power loop substrate on the metal layer, an upper switch on the power loop substrate, a lower switch on the power loop substrate and coupled to the upper switch, a capacitor on the power loop substrate and coupled to the upper switch, a first via through the power loop substrate and coupled between the lower switch and the metal layer, and a second via through the power loop substrate and coupled between the capacitor and the metal layer, wherein the power loop substrate has a height and separates the metal layer from the upper switch, lower switch and capacitor by the height.