Vertical Hall Element with Peripheral Electrode for Offset Correction
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Solution Overview
Problem
Vertical Hall elements experience significant challenges in accurately removing offset voltage due to structural asymmetry and variations in depletion layer width, leading to decreased magnetic sensitivity and increased chip size.
Innovation Solution
The vertical Hall element incorporates an outer peripheral electrode above a P-type well layer to reduce the depletion layer width near the surface, ensuring consistent current paths and enabling high-accuracy offset voltage removal using the spinning current method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the depletion layer width is reduced near the surface, then magnetic sensitivity is improved, but structural asymmetry and variations in depletion layer width cause offset voltage removal accuracy to deteriorate
Solution Approach 1:
The patent applies local quality by introducing an outer peripheral electrode specifically at the peripheral region of the well layer, creating a localized structure that modifies the depletion layer width only where needed. This localized modification ensures consistent depletion layer width at the periphery without affecting the overall magnetic sensitivity, while simultaneously improving offset voltage removal accuracy by addressing the specific issue of structural asymmetry at the boundaries.
2Area of stationary object
If the chip size is reduced, then integration density is improved, but offset voltage removal accuracy deteriorates due to structural asymmetry
Solution Approach 1:
The patent applies parameter changes by modifying the electrical parameters of the well layer structure through the introduction of the outer peripheral electrode. This changes the potential distribution and depletion layer characteristics in the peripheral region, enabling accurate offset voltage removal even in compact chip designs where structural asymmetry would otherwise be more pronounced.
3Manufacturing precision
If the depletion layer width is made consistent, then offset voltage removal accuracy is improved, but magnetic sensitivity may deteriorate
Solution Approach 1:
The patent resolves this contradiction by applying local quality - the outer peripheral electrode is positioned only at the periphery of the well layer, creating a localized modification that ensures consistent depletion layer width at the boundaries without uniformly affecting the entire active region. This localized approach maintains magnetic sensitivity in the central sensing area while achieving depletion layer width consistency at the periphery for accurate offset voltage removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances magnetic sensitivity and reduces chip size by maintaining consistent depletion layer width, allowing for precise offset voltage correction without interfering with current paths.
Implementation Method 1
an outer peripheral electrode, formed along an upper surface of the well layer via an insulating film
Implementation Method 2
vertical Hall elements that detect magnetic field components parallel to the surface of the semiconductor substrate
Data Source
AI summary
A vertical Hall element 100 formed on a surface of a P-type semiconductor substrate 10 includes: an N-type epitaxial layer 30 formed on the surface of the P-type semiconductor substrate 10; an electrode group 110, disposed on a surface of the N-type epitaxial layer 30 and formed by electrodes 111 to 115; a P-type well layer 50, disposed on the N-type epitaxial layer 30, and disposed in a ring shape on an outer periphery separate from the electrode group 110; and an outer peripheral electrode 120, formed along an upper surface of the P-type well layer 50 via an insulating film 60.