Vertical III-V Hall Sensor Epitaxy for Reliable Fabrication

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Solution Overview

Problem

Existing technologies have not been able to manufacture vertical Hall sensors using III-V materials due to incompatible manufacturing methods and technological requirements with silicon, preventing reliable and cost-effective production.

Innovation Solution

A vertical III-V Hall sensor design with a substrate layer, insulating layers, and III-V semiconductor layers manufactured through epitaxy processes, utilizing metal-organic precursors, allowing for monolithic growth and lattice-matched deposition without semiconductor bonds, and featuring structured contact regions and peripheral insulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertical Hall sensor structure is implemented with III-V materials, then sensitivity and manufacturing reliability are improved, but manufacturing compatibility and process feasibility deteriorate due to incompatible manufacturing methods with silicon

Engineering Contradiction:
Improvemanufacturing reliabilityVSAvoidmanufacturing compatibility
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the fundamental manufacturing parameters by adopting epitaxial growth methods (MOVPE, MBE) instead of silicon-compatible processes. This includes using metal-organic precursors for layer deposition, controlling temperature gradients for selective growth, and implementing in-situ doping during epitaxy to achieve the required n-doping in the III-V semiconductor layer without requiring post-growth implantation steps

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an insulating layer as an intermediary between the substrate and the III-V semiconductor layer, and between the semiconductor layer and contact regions. This insulating layer enables electrical isolation and facilitates the integration of III-V materials with silicon substrates despite their incompatible manufacturing requirements, acting as a buffer that accommodates different process conditions

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If doping is achieved through implantation, then doping precision is improved, but process feasibility deteriorates as implantation is not possible with III-V materials

Engineering Contradiction:
Improvedoping precisionVSAvoidprocess feasibility
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent performs doping during the epitaxial growth process itself, rather than as a subsequent implantation step. By incorporating dopants into the metal-organic precursors or introducing them during specific growth stages, the doping is established preliminarily during layer formation, ensuring uniform distribution and precise control without requiring post-growth modification steps that would be incompatible with III-V materials

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical implantation process with a chemical deposition approach where dopants are introduced through gas-phase precursors during epitaxial growth. This substitution eliminates the need for ion implantation equipment and processes, using instead chemical vapor deposition mechanisms to achieve controlled doping throughout the III-V semiconductor layer

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Object-affected harmful factors

If thermal passivation such as oxide growth is applied, then surface protection is improved, but process compatibility deteriorates as thermal passivation is not possible with III-V materials

Engineering Contradiction:
Improvesurface protectionVSAvoidprocess compatibility
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent employs a sacrificial organic layer deposited during epitaxy that serves as a temporary protective barrier. This layer is grown alongside the III-V semiconductor layer and can be selectively removed or modified in subsequent processing steps, providing surface protection during manufacturing without requiring permanent thermal passivation layers that would be incompatible with III-V material processing temperatures and conditions

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables reliable and cost-effective manufacturing of high-sensitivity vertical Hall sensors using III-V materials, overcoming technological barriers and enabling uniform thickness and doping control.

Implementation Method 1

The III-V semiconductor layers are manufactured by means of an epitaxy process, generally using metal-organic precursors, in particular, with the aid of an MOVPE or an MBE system

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

All layers can be manufactured by means of gas phase epitaxy in an MOVPE system

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS20260096352A1Vertical iii-v hall sensor
Publication Date: 2026.04.02 TDK MICRONAS GMBH
  • US20260096352A1 patent drawing
  • US20260096352A1 patent drawing

AI summary

A vertical III-V Hall sensor, which has a substrate layer with an upper side and an underside, and a first insulating layer formed on the substrate layer, and a III-V semiconductor layer formed on the insulating layer, and a second insulating layer formed on the III-V semiconductor layer, the second insulating layer being structured and having at least three openings designed as contact regions, and the III-V semiconductor layer having a length formed in the X direction and a width formed in the Y direction, and the at least three contact regions being arranged along a straight line, and the III-V semiconductor layer having an n doping, and the III-V semiconductor layer having a peripheral insulation.