Vertical HEMT-HHMT Channel Structure for High Breakdown Voltage
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Solution Overview
Problem
Existing semiconductor devices using group III nitride semiconductors face challenges in achieving high withstand voltage, low on-resistance, and high reliability while maintaining a compact device area, as increased device area and thickness lead to higher costs and reduced switching speed.
Innovation Solution
The semiconductor device structure involves forming a groove on a substrate with a hexagonal symmetrical lattice structure, growing a channel layer within the groove using a single crystal seed layer, and forming a barrier layer and two-dimensional electron or hole gas on the channel layer. Additionally, a bottom electrode is formed to adjust the electric field distribution, which helps in reducing the local electric field intensity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness or quality of the channel layer is increased in the longitudinal direction, then the withstand voltage is improved, but the device area and cost increase
Solution Approach 1:
The patent transitions from traditional planar device architecture to a vertical device structure by growing the channel layer along the c-axis direction perpendicular to the substrate. This vertical configuration allows the electric field to be distributed along the vertical dimension rather than requiring lateral expansion, thereby achieving high breakdown voltage without increasing device area. The vertical channel layer grown on a hexagonal groove structure enables this dimensional transition effectively.
2Reliability
If the length of the drift region is increased in the lateral direction, then the withstand voltage is improved, but the device area increases
Solution Approach 1:
The invention relocates the drift region functionality from the lateral plane to the vertical direction by forming the channel layer with controlled thickness along the c-axis. The vertical channel structure with optimized thickness achieves the same voltage blocking capability that would otherwise require a lengthy lateral drift region, thus reducing device footprint while maintaining withstand voltage performance.
3Reliability
If the device area is increased, then the withstand voltage is improved, but the switching speed is reduced
Solution Approach 1:
By configuring the channel layer vertically along the c-axis with optimized thickness, the patent achieves high breakdown voltage without the need for large device area. This compact vertical structure reduces the distance charges must travel during switching operations, thereby maintaining fast switching speed while achieving high withstand voltage capability.
4Reliability
If the channel layer thickness is increased, then the withstand voltage is improved, but the on-resistance increases
Solution Approach 1:
The patent optimizes the channel layer thickness to a specific range (50-200 nm) to achieve the optimal balance between withstand voltage and on-resistance. Additionally, the hexagonal groove structure and single crystal seed layer are employed to enhance carrier mobility, which compensates for the increased resistance from thicker channel layers, thereby achieving both high breakdown voltage and low on-resistance through parameter optimization and structural enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the realization of semiconductor devices with improved withstand voltage, reduced on-resistance, and enhanced reliability, while maintaining a compact device area, thus achieving high performance and cost-effectiveness.
Implementation Method 1
growing a channel layer along the groove by taking the single crystal seed layer as a core under restriction of the groove
Implementation Method 2
forming a barrier layer on the exposed channel layer, then forming a two-dimensional electron gas and immovable background positive charges on a first face of the channel layer
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a groove formed on the substrate, a channel layer structure grown under restriction of the groove structure, the channel layer structure being exposed from an upper surface of the substrate; a barrier layer covering the exposed channel layer structure, a two-dimensional electron gas and a two-dimensional hole gas respectively formed on a second face and a first face of the channel layer structure, and a source, a gate, and a drain formed on the first face/second face of the channel layer structure, and a bottom electrode formed on the second face/first face of the channel layer structure.