Vertical Heterojunction Tunnel FET Gate Field Alignment
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Solution Overview
Problem
Existing tunnel-FET designs with a perpendicular tunnel-junction reduce the effectiveness of the gate field, and those with a gate-parallel tunnel path either lack a heterojunction or have it on the drain side, leading to increased parasitic ambipolar current.
Innovation Solution
A vertical heterojunction tunnel field-effect transistor (FET) is fabricated using a silicon-on-insulator (SOI) substrate with a gate region, a drain region, and a vertical heterojunction source region, where the heterojunction is on the source side, generating a tunnel path inline with the gate field, thus suppressing parasitic ambipolar behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a perpendicular tunnel-junction is used, then the device structure is simplified, but the gate field effectiveness is reduced
Solution Approach 1:
The patent transitions from a conventional perpendicular tunnel-junction (one-dimensional alignment) to a gate-parallel tunnel path with vertical heterojunction (two-dimensional configuration). The tunnel path is oriented parallel to the gate field while the heterojunction interface is positioned vertically, creating a configuration where the tunneling occurs in the same dimension as the gate field, maximizing gate control effectiveness.
2Reliability
If a gate-parallel tunnel path with heterojunction is used, then gate field effectiveness is improved, but parasitic ambipolar current increases when heterojunction is on drain side
Solution Approach 1:
The patent applies heterojunction material composition selectively only in the source region adjacent to the gate, while the drain region maintains different material properties. This localized heterojunction configuration enables enhanced tunneling and gate control at the source without introducing parasitic ambipolar current paths at the drain, as the heterojunction is confined to where it provides benefit.
Solution Approach 2:
The device structure is made asymmetric by placing the heterojunction exclusively on the source side of the gate rather than symmetrically on both sides. This asymmetric configuration creates a directional tunneling path from source to drain that is controlled by the gate field, while preventing reverse ambipolar current flow that would occur with symmetric heterojunction placement.
3Reliability
If heterojunction is placed on drain side, then tunnel path is formed, but parasitic ambipolar behavior is suppressed less effectively
Solution Approach 1:
Instead of placing the heterojunction on the drain side as in conventional designs, the patent inverts the configuration by positioning the heterojunction on the source side adjacent to the gate. This inversion allows the tunnel path to form through the heterojunction interface while the gate field effectively controls and suppresses parasitic ambipolar behavior, as the heterojunction is now positioned where the gate can exert maximum control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a significant increase in drain current and subthreshold slope, with the tunnel path inline with the gate field enhancing performance by up to 100 times in drain current and 10,000 times in subthreshold slope compared to conventional designs.
Implementation Method 1
the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region
Data Source
AI summary
Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.