Vertical and Horizontal FET Integration on Common Substrate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in integrating vertical-type and horizontal-type transistors on the same device without compromising performance characteristics, particularly in achieving a reduced device footprint while maintaining necessary FET device performance.
Innovation Solution
A method of forming both vertical FET and horizontal FINFET devices on a common semiconductor substrate using sacrificial layers, hard masks, and high-k gate formation, with uniform gate heights and replacement gate material, allowing for the integration of L-shaped high-k metal gates and shared semiconductor processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical FET designs are used to reduce device footprint, then area is reduced, but device performance characteristics are compromised
Solution Approach 1:
The patent divides the transistor structure into vertical and horizontal segments, with vertical FETs providing high density and horizontal FINFETs providing performance characteristics. This segmentation allows each type to fulfill different functional requirements within the same device footprint.
Solution Approach 2:
The patent merges vertical FET and horizontal FINFET structures into a single integrated device, combining the area efficiency of vertical transistors with the performance characteristics of horizontal transistors to achieve both reduced footprint and maintained performance.
2Device complexity
If uniform gate heights are used for both vertical and horizontal devices, then manufacturing complexity is reduced, but device performance optimization is limited
Solution Approach 1:
The patent employs a universal gate formation process that serves multiple functions: it defines the channel length for both vertical and horizontal devices, establishes uniform threshold voltages, and simplifies manufacturing while maintaining performance through shared processing steps.
Solution Approach 2:
The patent utilizes parameter changes in the gate material (high-k dielectric) and gate structure configuration to achieve different electrical characteristics from a uniform physical structure, allowing performance optimization without increasing manufacturing complexity.
3Productivity
If shared sacrificial layers and hard masks are used for both device types, then manufacturing efficiency is improved, but device structure differentiation becomes challenging
Solution Approach 1:
The patent uses sacrificial layers and hard masks as intermediary structures that enable simultaneous formation of both vertical and horizontal device features through shared processing steps, while selective removal and transformation of these intermediaries create the required structural differentiation.
Solution Approach 2:
The patent performs preliminary patterning actions using hard masks and sacrificial layers before final device formation, allowing both device types to be defined early in the process through shared steps, with differentiation achieved through subsequent selective processing.
Data Source
AI summary
A method of forming a vertical FET device and a horizontal FINFET device on a common semiconductor substrate includes forming, on the semiconductor substrate, vertical device fins for the vertical FET device and the horizontal FINFET device with a sacrificial layer and a hard mask (HM) layer. The method also includes forming a vertical FET device doped source and drain (S/D) on the substrate, forming a shallow trench isolation (STI) and a bottom spacer, removing the HM layer and the sacrificial layer for horizontal FINFET device, and forming a sacrificial gate. The method further includes forming an oxide inter dielectric (ILD) layer, and opening the sacrificial gate, forming high-k vertical FET device gate and a high-k horizontal FINFET device gate, and forming contacts.