Vertical and Horizontal Gate Semiconductor Device Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Trench gate-type MOSFETs are limited to single-device applications due to the need for substrate connection at the drain terminal, preventing integration with horizontal-type devices and increasing chip area for high voltage and current capacity.
Innovation Solution
A semiconductor device with both vertical and horizontal type gates is developed, featuring channels and drains formed in a horizontal direction while maintaining a vertical channel structure, allowing for high integration and increased breakdown voltage through specific doping and oxide layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If trench gate-type MOSFET structure is used, then high integration and low source-drain on resistance are achieved, but the device cannot be integrated with horizontal-type devices and requires substrate connection at drain terminal
Solution Approach 1:
The patent merges the vertical gate structure and horizontal gate structure into a single semiconductor device. The vertical gate extends from the first surface through the semiconductor layer to the second surface, while horizontal gates are formed at different levels within the semiconductor layer, creating a three-dimensional integrated structure that combines both gate orientations
Solution Approach 2:
The patent transitions from traditional two-dimensional planar or trench gate structures to a three-dimensional structure by forming vertical gates that extend through the semiconductor layer thickness and horizontal gates at different depths, utilizing the third dimension (vertical depth) to achieve higher integration without compromising adaptability
2Power
If horizontal channels are formed in drain extended MOSFET, then high voltage and current capacity are achieved, but chip area is increased
Solution Approach 1:
The patent nests horizontal channels within the vertical gate structure. The horizontal channels are formed at different depth levels within the semiconductor layer, surrounded by the vertical gate, creating a nested configuration where the vertical gate envelops multiple horizontal channel regions, thereby achieving high power capacity in a compact volume
Solution Approach 2:
The semiconductor layer is structured with multiple voids and channels at different levels - horizontal channels for current flow and vertical trenches for gate formation. This porous-like three-dimensional structure increases the effective channel volume for power handling while maintaining a compact external footprint
Data Source
AI summary
A semiconductor device having both vertical and horizontal type gates and a method for fabricating the same for obtaining high integration of the semiconductor device and integration with other devices while also maximizing the breakdown voltage and operational speed and preventing damage to the semiconductor device.