Vertical Current-Path HV FET Structure for Surface Breakdown

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Solution Overview

Problem

High voltage field effect transistors face surface breakdown voltage issues due to complex extended low doped drain structures, which increase process complexity and cost.

Innovation Solution

A semiconductor structure with a shallow trench isolation structure, a gate stack structure, and epitaxial semiconductor material portions to reduce high voltage breakdown by increasing the total length of current paths within a smaller device area, including a dielectric gate spacer and source/drain regions with specific doping configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex extended low doped drain structures are used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but process complexity and manufacturing cost increase

Engineering Contradiction:
Improvesurface breakdown voltageVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the complex extended low doped drain structure from the device design. Instead of using the traditional complex LDD structure to improve surface breakdown characteristics, the invention employs a simplified structure that achieves the same reliability improvement through a different approach, thereby reducing process complexity and manufacturing cost while maintaining enhanced surface breakdown voltage performance

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If complex extended low doped drain structures are used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but manufacturing cost increases

Engineering Contradiction:
Improvesurface breakdown voltageVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent removes the complex extended low doped drain structure that drives up manufacturing costs. The simplified structure design requires fewer fabrication steps and less complex processing, directly reducing manufacturing cost while still achieving improved surface breakdown voltage characteristics through alternative structural arrangements

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention changes key structural parameters such as doping concentration distributions and geometric dimensions to achieve improved surface breakdown voltage without requiring complex extended low doped drain structures. By optimizing these parameters in a simplified structure, the patent achieves both reliability improvement and cost reduction

Inventive Principle:
Principle #35Parameter changes

3Reliability

If larger device area is used to accommodate complex structures, then high voltage breakdown performance is improved, but device area increases

Engineering Contradiction:
Improvehigh voltage breakdown performanceVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from horizontal current paths to vertical current paths in the device structure. This dimensional change allows the current to flow vertically through the device, enabling improved high voltage breakdown performance within a smaller lateral footprint. The vertical architecture efficiently utilizes the third dimension to achieve better breakdown characteristics without increasing the device's planar area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11978774B2High voltage field effect transistor with vertical current paths and method of making the same
Publication Date: 2024.05.07 SANDISK TECHNOLOGIES LLC
  • US11978774B2 patent drawing
  • US11978774B2 patent drawing
  • US11978774B2 patent drawing

AI summary

A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.