Vertical IGBT Dual Gate Segmentation Hot Hole Prevention
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Solution Overview
Problem
Semiconductor devices face instability and reliability issues due to dynamic avalanche phenomena and hot hole passage through insulating layers during turn-off operations, leading to degraded characteristics and extended switching times.
Innovation Solution
The semiconductor device incorporates a specific configuration of conductive members, semiconductor regions, and insulating members with varying thicknesses and conductivity types, where the first conductive member is set to the off-state before the second conductive member, and the insulating member thicknesses are optimized to prevent hot hole passage, maintaining stable operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional IGBT structure is used, then the device can operate, but it suffers from dynamic avalanche phenomena and hot hole passage through insulating layers during turn-off, leading to unstable operations and degraded characteristics
Solution Approach 1:
The gate structure is segmented into two independent gates (first gate and second gate) with different conductivity types. The first gate controls the first insulating layer interface while the second gate controls the second insulating layer interface. This segmentation allows independent control of electric fields at different interfaces, preventing simultaneous breakdown and hot hole injection that occurs in conventional single-gate structures during dynamic avalanche conditions
Solution Approach 2:
The patent introduces an intermediary structure consisting of two insulating layers with different thicknesses positioned between the gates and semiconductor regions. The first insulating layer (thinner) and second insulating layer (thicker) act as intermediaries that distribute and control the electric field distribution during turn-off, preventing direct hot hole injection into the insulating layers while maintaining necessary electric field strength for device operation
2Object-affected harmful factors
If the insulating layer thickness is increased to prevent hot hole passage, then hot hole injection is reduced, but the device loses control over electric field distribution and cannot effectively suppress dynamic avalanche phenomena
Solution Approach 1:
The patent applies local quality by making the first insulating layer thinner than the second insulating layer. The thinner first insulating layer is positioned where higher electric field control is needed to suppress dynamic avalanche, while the thicker second insulating layer provides better protection against hot hole injection at its interface. This non-uniform thickness distribution optimizes both avalanche control and hot hole prevention in different locations
3Productivity
If both gates are turned off simultaneously, then the device turns off completely, but this causes extended switching times and increased loss during the turn-off transition
Solution Approach 1:
The patent implements preliminary action by turning off the first gate before the second gate during the turn-off sequence. The first gate (controlling the first insulating layer interface) is deactivated first to prepare the electric field distribution, followed by turning off the second gate. This sequential preliminary action prevents simultaneous breakdown at both interfaces, reducing switching time and energy loss during the transition
Data Source
AI summary
According to one embodiment, a semiconductor device includes first, and second conductive members, a first electrode including first and second electrode regions, a second electrode electrically connected to a first semiconductor film portion, a first semiconductor region including first to fourth partial regions, a second semiconductor region including the first semiconductor film portion, a third semiconductor region including a first semiconductor layer portion, a fourth semiconductor region provided between the first electrode and the first semiconductor region, and a first insulating member including insulating portions. The first partial region is between the first electrode region and the first conductive member. The second partial region is between the second electrode region and the second conductive member. The third partial region is between the first and second partial regions and between the first electrode and the fourth partial region. The fourth partial region is between the first and second conductive members.


