Vertical IGBT with RESURF Epitaxial Layer for Field Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor apparatuses with vertical type semiconductor devices, the formation of a region with high concentrations of impurities in the peripheral region leads to crystal defects and potential current leakage, while increasing n-type impurity concentration in the n-type region to suppress electric field concentration results in decreased breakdown voltage characteristics.

Innovation Solution

The use of an epitaxial layer in the peripheral region with a high concentration of second conductivity type impurities, formed without reaching the base semiconductor layer, reduces crystal defects and maintains high breakdown voltage characteristics by suppressing electric field concentration at the upper surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the concentration of n-type impurities in the n-type region is increased to suppress electric field concentration, then electric field distribution is improved, but breakdown voltage characteristics decrease

Engineering Contradiction:
Improveelectric field distributionVSAvoidbreakdown voltage
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent introduces a peripheral region with a specific impurity concentration profile that differs from the device region. The n-type region in the peripheral region has a higher impurity concentration than the drift region, creating a localized structure that suppresses electric field concentration at the upper surface without affecting the breakdown voltage determined by the device region. This local differentiation resolves the contradiction by allowing electric field control in one area without compromising the overall breakdown characteristics.

Inventive Principle:
Principle #3Local quality

2Reliability

If a region with high concentration of impurities is formed in the peripheral region to suppress electric field concentration, then electric field distribution is improved, but crystal defects increase and current leakage occurs

Engineering Contradiction:
Improveelectric field distributionVSAvoidcrystal defects and current leakage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent carefully controls the impurity concentration parameters in the peripheral region. The n-type region has a concentration higher than the drift region but lower than the device region's body region. By optimizing this intermediate concentration level, the patent achieves sufficient electric field suppression without creating excessive crystal defects or current leakage pathways that would result from overly high impurity concentrations.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively minimizes crystal defects and maintains superior breakdown voltage characteristics by forming a high-concentration epitaxial layer in the peripheral region, reducing the likelihood of electric field disturbances and current leakage.

Implementation Method 1

suppressing electric field concentration at the upper surface

Methodology Applied
Scientific EffectElectric field: Electric Field

Implementation Method 2

The use of an epitaxial layer in the peripheral region with a high concentration of second conductivity type impurities

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9000478B2Vertical IGBT adjacent a RESURF region
Publication Date: 2015.04.07 DENSO CORP
  • US9000478B2 patent drawing
  • US9000478B2 patent drawing
  • US9000478B2 patent drawing

AI summary

A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.