Vertical IGFET Dopant Profile Optimization for Power Chip Integration
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Solution Overview
Problem
Existing semiconductor technologies face challenges in integrating vertical insulated gate field effect transistors (IGFETs) with other semiconductor components, such as sensors, in a power chip, requiring improved flexibility and efficiency in dopant profiles to optimize performance and breakdown voltage.
Innovation Solution
A semiconductor device with a vertical IGFET in one area and a further semiconductor component in another area, featuring distinct dopant profiles: a declining dopant profile near the drain electrode and a broadened peak dopant profile near the body zone, with trenches and junction isolation zones to enhance electrical connectivity and breakdown voltage, manufactured through epitaxial growth and thermal diffusion processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a uniform dopant profile is used in the drift zone, then the manufacturing process is simple, but the on-state resistance cannot be optimized and breakdown voltage is limited
Solution Approach 1:
The drift zone is divided into multiple regions with different dopant concentrations: a first region with lower dopant concentration and a second region with higher dopant concentration. This local differentiation allows optimization of on-state resistance in the high-field region while maintaining breakdown voltage, resolving the contradiction between performance optimization and manufacturing simplicity.
Solution Approach 2:
The patent changes the dopant concentration parameter along the vertical direction of the drift zone, creating a graded or multi-level dopant profile. This parameter variation enables simultaneous optimization of electrical performance (lower on-state resistance) and breakdown voltage, overcoming the limitation of uniform dopant profiles.
2Adaptability or versatility
If vertical IGFETs are integrated with other semiconductor components, then functionality is enhanced, but manufacturing flexibility and performance optimization become more difficult
Solution Approach 1:
The semiconductor device is segmented into distinct functional regions: a first area containing the vertical IGFET with optimized dopant profile, and a second area for other semiconductor components. This segmentation allows independent optimization of each component while maintaining overall integration, resolving the contradiction between versatility and manufacturing ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for optimized on-state resistance and improved flexibility in integrating IGFETs with other components, enhancing the performance and breakdown voltage of power chips while maintaining high dopant concentration and electrical isolation.
Implementation Method 1
introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer
Implementation Method 2
forming a first semiconductor layer on a semiconductor substrate
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area, introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer, and forming trenches in the second semiconductor layer in the continuous first area.