Vertical Impact Ionization MOSFET Subthreshold Slope
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Solution Overview
Problem
Conventional MOSFET devices face challenges in scaling down due to the 60 mV/decade room temperature limit for subthreshold slope, and impact ionization devices require complex processing and larger chip space, with high threshold voltages that are difficult to manage using current techniques.
Innovation Solution
The development of recessed and vertical impact ionization MOSFET (I-MOS) devices with germanium or silicon germanium impact ionization regions, allowing for a simpler process flow and reduced dimensions, featuring oppositely doped source and drain regions and a gap between the source region and gate, which reduces the threshold voltage and subthreshold slope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOSFET devices are scaled down to nanoscale region, then device density increases, but subthreshold slope is limited to 60 mV/decade
Solution Approach 1:
The patent changes the doping configuration parameter from conventional NPN/PNP to NNP/PPN, creating a lightly-doped channel region that enables impact ionization. This parameter change allows the device to achieve subthreshold slopes below the conventional 60 mV/decade limit while maintaining scaled dimensions
Solution Approach 2:
The patent employs composite material structures including germanium or silicon germanium in the impact ionization region combined with silicon substrate. This composite approach enables lower threshold voltages and improved subthreshold characteristics while maintaining compatibility with conventional processing
2Reliability
If planar impact ionization devices are used to achieve lower subthreshold slope, then switching performance improves, but chip surface area increases
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional vertical structure by extending the channel vertically above the substrate. This dimensional change allows the device to achieve impact ionization characteristics in a compact footprint, reducing the chip surface area required while maintaining improved subthreshold slope performance
3Reliability
If germanium or silicon germanium is used for impact ionization regions, then threshold voltage decreases, but manufacturing complexity increases
Solution Approach 1:
The patent applies germanium or silicon germanium selectively in the impact ionization region rather than throughout the entire device. This localized material application achieves the desired threshold voltage reduction while minimizing manufacturing complexity by limiting the use of difficult-to-process materials to only where they are most effective
4Area of stationary object
If L-shaped impact ionization transistors are created to reduce space, then chip footprint decreases, but process complexity increases
Solution Approach 1:
The patent employs a vertical channel structure that extends perpendicular to the substrate surface, achieving compact footprint without requiring complex L-shaped lateral configurations. This vertical approach simplifies the fabrication process by using straightforward epitaxial growth and doping techniques rather than complex spacer and etch sequences required for L-shaped devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These devices achieve a faster transition from the 'off' to 'on' state with a subthreshold slope of approximately 5 mV/decade or less, maintaining or reducing chip footprint while lowering threshold voltage without the need for voltage biasing schemes, and are scalable to dimensions of 100 nm or less.
Implementation Method 1
Devices have been proposed that use impact ionization to switch from the off to the on state. Such impact ionization devices may exhibit a subthreshold slope much lower than kT/q.
Data Source
AI summary
Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSFET devices while maintaining a footprint equal to or less than conventional MOSFET devices.